[PATCH] D146031: [AMDGPU] Add MMOs for GFX11 Streamout Instructions

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/docs/AMDGPUUsage.rst:788
+**Streamout Registers**
+  Dedicated registers used by the GS NGG Streamout Instructions.
+
----------------
rovka wrote:
> t-tye wrote:
> > My understanding is that address spaces are about memory, not registers. So why is an address space being used for this purpose? Is it that the values are being passed in memory?
> I think the idea is that these registers are embedded into the GDS. 
> 
> In principle, we could use the region address space and as far as the existing tests are concerned we'd get the same results, but the docs are pretty clear that these are not operating on GDS directly, so it seemed cleaner to have a new address space.
> 
> I'm open to other interpretations :)
> My understanding is that address spaces are about memory, not registers. So why is an address space being used for this purpose? Is it that the values are being passed in memory?

They are called "registers" in the documentation but as far as the ISA is concerned they act more like memory in a separate address space that does not interact with any other type of memory. The only instructions that access them take an offset into the "register" file and read or write 32 or 64 bits at that offset. The individual registers are not named. Read operations from the register file use LGKMcnt to track when the read has completed.

I guess all of this *could* be implemented by modelling them as individual registers, but my hunch is that it would be more complicated to implement for no practical benefit.


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https://reviews.llvm.org/D146031