[llvm] cf40b8a - [RISCV] Pass vector argument by stack correctly.
Kito Cheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 02:22:55 PDT 2023
Author: Kito Cheng
Date: 2023-03-15T17:22:47+08:00
New Revision: cf40b8a4dd3db7370f4cde8415a05eed07ba711a
URL: https://github.com/llvm/llvm-project/commit/cf40b8a4dd3db7370f4cde8415a05eed07ba711a
DIFF: https://github.com/llvm/llvm-project/commit/cf40b8a4dd3db7370f4cde8415a05eed07ba711a.diff
LOG: [RISCV] Pass vector argument by stack correctly.
We've a argument lowering logic to prevent floating-point value pass
passed with bit-conversion, but that rule should not applied to vector
arguments.
---
How to pass argument to `foo`:
```
tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer)
```
`foo` take 13 arguments, first 8 argument pass in GPR, and next 2 LMUL 8 vector
arguments passed in v8-v23, and now we run out of argument register for GPR and
vector register, so we must pass last LMUL 8 vector argument by stack.
Which means we should reserve `vlenb * 8` byte for stack for the last
vector argument.
Reviewed By: craig.topper, asb
Differential Revision: https://reviews.llvm.org/D145938
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7846feebfe2b9..24896de16d275 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12794,9 +12794,10 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
return false;
}
- // When a floating-point value is passed on the stack, no bit-conversion is
- // needed.
- if (ValVT.isFloatingPoint()) {
+ // When a scalar floating-point value is passed on the stack, no
+ // bit-conversion is needed.
+ if (ValVT.isFloatingPoint() && LocInfo != CCValAssign::Indirect) {
+ assert(!ValVT.isVector());
LocVT = ValVT;
LocInfo = CCValAssign::Full;
}
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll b/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
index 2138c88c97260..3e2af11365297 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
@@ -1,16 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -treat-scalable-fixed-error-as-warning < %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; CHECK: warning: Invalid size request on a scalable vector
+; CHECK-NOT: warning: Invalid size request on a scalable vector
define void @bar() nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -96
+; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 96
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: andi sp, sp, -64
+; CHECK-NEXT: mv s1, sp
; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vs8r.v v8, (sp)
+; CHECK-NEXT: addi a0, s1, 64
+; CHECK-NEXT: vs8r.v v8, (a0)
+; CHECK-NEXT: sd a0, 0(sp)
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: li a2, 0
@@ -21,8 +32,12 @@ define void @bar() nounwind {
; CHECK-NEXT: li a7, 0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: call foo at plt
-; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, s0, -96
+; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret
entry:
tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, <vscale x 16 x float> zeroinitializer, <vscale x 16 x float> zeroinitializer, <vscale x 16 x float> zeroinitializer)
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