[llvm] 7ada7bb - [Target] Use *{Set,Map}::contains (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 14 18:07:15 PDT 2023
Author: Kazu Hirata
Date: 2023-03-14T18:06:55-07:00
New Revision: 7ada7bbee17f7cd995882dfcc3ac9fa32daf1a4f
URL: https://github.com/llvm/llvm-project/commit/7ada7bbee17f7cd995882dfcc3ac9fa32daf1a4f
DIFF: https://github.com/llvm/llvm-project/commit/7ada7bbee17f7cd995882dfcc3ac9fa32daf1a4f.diff
LOG: [Target] Use *{Set,Map}::contains (NFC)
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/lib/Target/BPF/BTFDebug.cpp
llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index aba632aa5a039..1cff11227cf94 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5263,10 +5263,10 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
#undef PARSE_BITS_ENTRY
}
- if (Seen.find(".amdhsa_next_free_vgpr") == Seen.end())
+ if (!Seen.contains(".amdhsa_next_free_vgpr"))
return TokError(".amdhsa_next_free_vgpr directive is required");
- if (Seen.find(".amdhsa_next_free_sgpr") == Seen.end())
+ if (!Seen.contains(".amdhsa_next_free_sgpr"))
return TokError(".amdhsa_next_free_sgpr directive is required");
unsigned VGPRBlocks;
@@ -5304,7 +5304,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
UserSGPRCount);
if (isGFX90A()) {
- if (Seen.find(".amdhsa_accum_offset") == Seen.end())
+ if (!Seen.contains(".amdhsa_accum_offset"))
return TokError(".amdhsa_accum_offset directive is required");
if (AccumOffset < 4 || AccumOffset > 256 || (AccumOffset & 3))
return TokError("accum_offset should be in range [4..256] in "
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 1a951c1ab02fb..d361df26841c3 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -1656,7 +1656,7 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
for (unsigned i = 0; i < 4; i++) {
unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
- if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
+ if (SwizzleRemap.contains(Idx))
Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
}
@@ -1664,7 +1664,7 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
for (unsigned i = 0; i < 4; i++) {
unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
- if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
+ if (SwizzleRemap.contains(Idx))
Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 4056274cd4404..7f874b245b8f4 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -328,7 +328,7 @@ R600InstrInfo::ExtractSrcs(MachineInstr &MI,
if (Reg == R600::OQAP) {
Result.push_back(std::pair(Index, 0U));
}
- if (PV.find(Reg) != PV.end()) {
+ if (PV.contains(Reg)) {
// 255 is used to tells its a PS/PV reg
Result.push_back(std::pair(255, 0U));
continue;
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 962f3383146c0..536efbbfd9cb7 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -2092,7 +2092,7 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
// Step1: Find the base-registers and a 64bit constant offset.
MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
MemAddress MAddr;
- if (Visited.find(&MI) == Visited.end()) {
+ if (!Visited.contains(&MI)) {
processBaseWithConstOffset(Base, MAddr);
Visited[&MI] = MAddr;
} else
@@ -2155,7 +2155,7 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
const MachineOperand &BaseNext =
*TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr);
MemAddress MAddrNext;
- if (Visited.find(&MINext) == Visited.end()) {
+ if (!Visited.contains(&MINext)) {
processBaseWithConstOffset(BaseNext, MAddrNext);
Visited[&MINext] = MAddrNext;
} else
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 80d500d52c709..c7ac0de07a7b7 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -578,7 +578,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
// Check if an entry created for \p Reg in PrologEpilogSGPRSpills. Return true
// on success and false otherwise.
bool hasPrologEpilogSGPRSpillEntry(Register Reg) const {
- return PrologEpilogSGPRSpills.find(Reg) != PrologEpilogSGPRSpills.end();
+ return PrologEpilogSGPRSpills.contains(Reg);
}
// Get the scratch SGPR if allocated to save/restore \p Reg.
diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp
index bde5f5db99e7f..e1a3e08d95b63 100644
--- a/llvm/lib/Target/BPF/BTFDebug.cpp
+++ b/llvm/lib/Target/BPF/BTFDebug.cpp
@@ -982,7 +982,7 @@ std::string BTFDebug::populateFileContent(const DISubprogram *SP) {
FileName = std::string(File->getFilename());
// No need to populate the contends if it has been populated!
- if (FileContent.find(FileName) != FileContent.end())
+ if (FileContent.contains(FileName))
return FileName;
std::vector<std::string> Content;
diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index fe723a4ba3fbf..a7887712c29a4 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -336,7 +336,7 @@ void Simplifier::Context::initialize(Instruction *Exp) {
while (!Q.empty()) {
Value *V = Q.pop_front_val();
- if (M.find(V) != M.end())
+ if (M.contains(V))
continue;
if (Instruction *U = dyn_cast<Instruction>(V)) {
if (isa<PHINode>(U) || U->getParent() != Block)
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index bb8f5c27e7b66..b2db77a531107 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -700,7 +700,7 @@ static bool useFuncSeen(const Constant *C,
const Function *caller = bb->getParent();
if (!caller)
continue;
- if (seenMap.find(caller) != seenMap.end())
+ if (seenMap.contains(caller))
return true;
}
}
@@ -753,7 +753,7 @@ void NVPTXAsmPrinter::emitDeclarations(const Module &M, raw_ostream &O) {
// If a caller has already been seen, then the caller is
// appearing in the module before the callee. so print out
// a declaration for the callee.
- if (seenMap.find(caller) != seenMap.end()) {
+ if (seenMap.contains(caller)) {
emitDeclaration(&F, O);
break;
}
diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
index 8710956e47ec8..f29a7af1bdf1c 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -910,7 +910,7 @@ bool PPCLoopInstrFormPrep::prepareBaseForDispFormChain(Bucket &BucketChain,
unsigned Remainder = cast<SCEVConstant>(BucketChain.Elements[j].Offset)
->getAPInt()
.urem(Form);
- if (RemainderOffsetInfo.find(Remainder) == RemainderOffsetInfo.end())
+ if (!RemainderOffsetInfo.contains(Remainder))
RemainderOffsetInfo[Remainder] = std::make_pair(j, 1);
else
RemainderOffsetInfo[Remainder].second++;
@@ -933,7 +933,7 @@ bool PPCLoopInstrFormPrep::prepareBaseForDispFormChain(Bucket &BucketChain,
// 1 X form.
unsigned MaxCountRemainder = 0;
for (unsigned j = 0; j < (unsigned)Form; j++)
- if ((RemainderOffsetInfo.find(j) != RemainderOffsetInfo.end()) &&
+ if ((RemainderOffsetInfo.contains(j)) &&
RemainderOffsetInfo[j].second >
RemainderOffsetInfo[MaxCountRemainder].second)
MaxCountRemainder = j;
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 3508194887143..dd5b885701fa9 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -7580,10 +7580,10 @@ static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
if (MI->getOperand(4).getImm() == (CCValid ^ CCMask))
std::swap(TrueReg, FalseReg);
- if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end())
+ if (RegRewriteTable.contains(TrueReg))
TrueReg = RegRewriteTable[TrueReg].first;
- if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end())
+ if (RegRewriteTable.contains(FalseReg))
FalseReg = RegRewriteTable[FalseReg].second;
DebugLoc DL = MI->getDebugLoc();
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
index 71b930022214e..82b016df2f648 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
@@ -580,7 +580,7 @@ Function *WebAssemblyLowerEmscriptenEHSjLj::getInvokeWrapper(CallBase *CI) {
FunctionType *CalleeFTy = CI->getFunctionType();
std::string Sig = getSignature(CalleeFTy);
- if (InvokeWrappers.find(Sig) != InvokeWrappers.end())
+ if (InvokeWrappers.contains(Sig))
return InvokeWrappers[Sig];
// Put the pointer to the callee as first argument
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a8c37db67f4d0..e9a069b7295e1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35961,10 +35961,10 @@ static MachineInstrBuilder createPHIsForCMOVsInSinkBB(
if (MIIt->getOperand(3).getImm() == OppCC)
std::swap(Op1Reg, Op2Reg);
- if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
+ if (RegRewriteTable.contains(Op1Reg))
Op1Reg = RegRewriteTable[Op1Reg].first;
- if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
+ if (RegRewriteTable.contains(Op2Reg))
Op2Reg = RegRewriteTable[Op2Reg].second;
MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
diff --git a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
index 5d9a9231fea9b..079d260e1fb5e 100644
--- a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
@@ -362,7 +362,7 @@ X86LoadValueInjectionLoadHardeningPass::getGadgetGraph(
SmallSet<NodeId, 8> UsesVisited, DefsVisited;
std::function<void(NodeAddr<DefNode *>)> AnalyzeDefUseChain =
[&](NodeAddr<DefNode *> Def) {
- if (Transmitters.find(Def.Id) != Transmitters.end())
+ if (Transmitters.contains(Def.Id))
return; // Already analyzed `Def`
// Use RDF to find all the uses of `Def`
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