[PATCH] D145687: [BOLT] Add minimal RISC-V 64-bit support
Amir Ayupov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 14 17:39:47 PDT 2023
Amir added a comment.
Thank you for working on it! Would you want to add a line to bolt/CODE_OWNERS.TXT?
================
Comment at: bolt/include/bolt/Core/BinaryFunction.h:1311
+ void addRelocationRISCV(uint64_t Offset, MCSymbol *Symbol, uint64_t RelType,
+ uint64_t Addend, uint64_t Value) {
----------------
Please move it to RISCVMCPlusBuilder, similar to D131813.
================
Comment at: bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp:35
+
+ bool hasEVEXEncoding(const MCInst &Inst) const override { return false; }
+
----------------
Feel free to remove these per D145972
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https://reviews.llvm.org/D145687/new/
https://reviews.llvm.org/D145687
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