[PATCH] D146008: [RISCV][NFC] Combine identical switch cases in TTI

[Ben Shi via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcb45be2b4f62: [RISCV][NFC] Combine identical switch cases in TTI (authored by benshi001).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146008/new/

https://reviews.llvm.org/D146008

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp


Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -876,7 +876,9 @@
   case Intrinsic::sadd_sat:
   case Intrinsic::ssub_sat:
   case Intrinsic::uadd_sat:
-  case Intrinsic::usub_sat: {
+  case Intrinsic::usub_sat:
+  case Intrinsic::fabs:
+  case Intrinsic::sqrt: {
     auto LT = getTypeLegalizationCost(RetTy);
     if (ST->hasVInstructions() && LT.second.isVector())
       return LT.first;
@@ -891,13 +893,6 @@
     }
     break;
   }
-  case Intrinsic::fabs:
-  case Intrinsic::sqrt: {
-    auto LT = getTypeLegalizationCost(RetTy);
-    if (ST->hasVInstructions() && LT.second.isVector())
-      return LT.first;
-    break;
-  }
   // TODO: add more intrinsic
   case Intrinsic::experimental_stepvector: {
     unsigned Cost = 1; // vid


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