[PATCH] D145972: [BOLT][NFC] Provide default impl for MIB methods that are only overridden on X86

[Amir Ayupov via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4e99891e7085: [BOLT][NFC] Provide default impl for MIB methods that are only overridden on X86 (authored by Amir).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145972/new/

https://reviews.llvm.org/D145972

Files:
  bolt/include/bolt/Core/MCPlusBuilder.h
  bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp


Index: bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -45,8 +45,6 @@
                                  *AArch64ExprB.getSubExpr(), Comp);
   }
 
-  bool hasEVEXEncoding(const MCInst &) const override { return false; }
-
   bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override {
     return false;
   }
@@ -1091,14 +1089,6 @@
     return true;
   }
 
-  bool isMoveMem2Reg(const MCInst &Inst) const override { return false; }
-
-  bool isLeave(const MCInst &Inst) const override { return false; }
-
-  bool isPop(const MCInst &Inst) const override { return false; }
-
-  bool isPrefix(const MCInst &Inst) const override { return false; }
-
   bool createReturn(MCInst &Inst) const override {
     Inst.setOpcode(AArch64::RET);
     Inst.clear();
Index: bolt/include/bolt/Core/MCPlusBuilder.h
===================================================================
--- bolt/include/bolt/Core/MCPlusBuilder.h
+++ bolt/include/bolt/Core/MCPlusBuilder.h
@@ -497,15 +497,9 @@
     return false;
   }
 
-  virtual bool isPrefix(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isPrefix(const MCInst &Inst) const { return false; }
 
-  virtual bool isRep(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isRep(const MCInst &Inst) const { return false; }
 
   virtual bool deleteREPPrefix(MCInst &Inst) const {
     llvm_unreachable("not implemented");
@@ -516,10 +510,7 @@
     return Inst.getOpcode() == TargetOpcode::EH_LABEL;
   }
 
-  virtual bool isPop(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isPop(const MCInst &Inst) const { return false; }
 
   /// Return true if the instruction is used to terminate an indirect branch.
   virtual bool isTerminateBranch(const MCInst &Inst) const {
@@ -556,10 +547,7 @@
     return false;
   }
 
-  virtual bool isLeave(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isLeave(const MCInst &Inst) const { return false; }
 
   virtual bool isADRP(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
@@ -575,10 +563,7 @@
     llvm_unreachable("not implemented");
   }
 
-  virtual bool isMoveMem2Reg(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isMoveMem2Reg(const MCInst &Inst) const { return false; }
 
   virtual bool isLoad(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
@@ -862,10 +847,7 @@
   }
 
   /// Return true if the instruction is encoded using EVEX (AVX-512).
-  virtual bool hasEVEXEncoding(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool hasEVEXEncoding(const MCInst &Inst) const { return false; }
 
   /// Return true if a pair of instructions represented by \p Insts
   /// could be fused into a single uop.


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