[llvm] 0ddc283 - [RISCV] A at plt-B+C: emit R_RISCV_PLT32 even if A is defined

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2023-03-14T15:16:58-07:00
New Revision: 0ddc283a29a7a2d5415a3d363396e39c262a5dc2

URL: https://github.com/llvm/llvm-project/commit/0ddc283a29a7a2d5415a3d363396e39c262a5dc2
DIFF: https://github.com/llvm/llvm-project/commit/0ddc283a29a7a2d5415a3d363396e39c262a5dc2.diff

LOG: [RISCV] A at plt-B+C: emit R_RISCV_PLT32 even if A is defined

Follow-up to D143226

Currently we incorrectly emit R_RISCV_ADD32/R_RISCV_SUB32.
Emit R_RISCV_PLT32 instead. The new behavior matches x86-64 and AArch64.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
    llvm/test/MC/RISCV/elf-reloc-plt32.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 40f38ee1dd758..41399b231519f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -140,6 +140,10 @@ bool RISCVELFStreamer::requiresFixups(MCContext &C, const MCExpr *Value,
                              MCConstantExpr::create(E.getConstant(), C), C);
   RHS = E.getSymB();
 
+  // Avoid ADD/SUB if Kind is not VK_None, e.g. A at plt - B + C.
+  if (E.getSymA()->getKind() != MCSymbolRefExpr::VK_None)
+    return false;
+
   // If either symbol is in a text section, we need to delay the relocation
   // evaluation as relaxation may alter the size of the symbol.
   //

diff  --git a/llvm/test/MC/RISCV/elf-reloc-plt32.s b/llvm/test/MC/RISCV/elf-reloc-plt32.s
index 8f3a40d36a390..f93262a138a91 100644
--- a/llvm/test/MC/RISCV/elf-reloc-plt32.s
+++ b/llvm/test/MC/RISCV/elf-reloc-plt32.s
@@ -3,9 +3,14 @@
 # RUN: llvm-mc -triple=riscv32 -filetype=obj %s -o - \
 # RUN:   | llvm-readobj -r - | FileCheck %s
 
+.globl func
+func:
+
 .data
 .word extern_func at PLT - . + 4
+.word func at PLT - . + 8
 
 # CHECK:      Section ({{.*}}) .rela.data {
 # CHECK-NEXT:   0x0 R_RISCV_PLT32 extern_func 0x4
+# CHECK-NEXT:   0x4 R_RISCV_PLT32 func 0x8
 # CHECK-NEXT: }