[llvm] 99b22a6 - [MSAN] Add (fixed) vector load/store test coverage [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 14 11:25:53 PDT 2023
Author: Philip Reames
Date: 2023-03-14T11:25:45-07:00
New Revision: 99b22a6cbfa019d231bc064d3bc1ba9d505f7604
URL: https://github.com/llvm/llvm-project/commit/99b22a6cbfa019d231bc064d3bc1ba9d505f7604
DIFF: https://github.com/llvm/llvm-project/commit/99b22a6cbfa019d231bc064d3bc1ba9d505f7604.diff
LOG: [MSAN] Add (fixed) vector load/store test coverage [nfc]
Added:
llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll b/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
new file mode 100644
index 0000000000000..52c60e9b83b29
--- /dev/null
+++ b/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
@@ -0,0 +1,280 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning"
+; RUN: opt < %s -msan-check-access-address=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=ADDR --implicit-check-not="call void @__msan_warning"
+; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=ORIGINS --implicit-check-not="call void @__msan_warning"
+
+target triple = "x86_64-unknown-linux-gnu"
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @load.v1i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @load.v1i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[P:%.*]], align 4
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @load.v1i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[P:%.*]], align 4
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @load.v1i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[P:%.*]], align 4
+; ORIGINS-NEXT: ret void
+;
+ load <1 x i32>, ptr %p
+ ret void
+}
+
+define void @load.v2i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @load.v2i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 8
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @load.v2i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 8
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @load.v2i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 8
+; ORIGINS-NEXT: ret void
+;
+ load <2 x i32>, ptr %p
+ ret void
+}
+
+define void @load.v4i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @load.v4i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 16
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @load.v4i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 16
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @load.v4i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 16
+; ORIGINS-NEXT: ret void
+;
+ load <4 x i32>, ptr %p
+ ret void
+}
+
+define void @load.v8i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @load.v8i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 32
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @load.v8i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 32
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @load.v8i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[P:%.*]], align 32
+; ORIGINS-NEXT: ret void
+;
+ load <8 x i32>, ptr %p
+ ret void
+}
+
+define void @load.v16i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @load.v16i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[P:%.*]], align 64
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @load.v16i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[P:%.*]], align 64
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @load.v16i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[P:%.*]], align 64
+; ORIGINS-NEXT: ret void
+;
+ load <16 x i32>, ptr %p
+ ret void
+}
+
+
+define void @store.v1i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @store.v1i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[TMP3]], align 4
+; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @store.v1i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ADDR-NEXT: store <1 x i32> zeroinitializer, ptr [[TMP3]], align 4
+; ADDR-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @store.v1i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; ORIGINS-NEXT: store <1 x i32> zeroinitializer, ptr [[TMP3]], align 4
+; ORIGINS-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4
+; ORIGINS-NEXT: ret void
+;
+ store <1 x i32> zeroinitializer, ptr %p
+ ret void
+}
+
+define void @store.v2i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @store.v2i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP3]], align 8
+; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @store.v2i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ADDR-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP3]], align 8
+; ADDR-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @store.v2i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; ORIGINS-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP3]], align 8
+; ORIGINS-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8
+; ORIGINS-NEXT: ret void
+;
+ store <2 x i32> zeroinitializer, ptr %p
+ ret void
+}
+
+define void @store.v4i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @store.v4i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP3]], align 16
+; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @store.v4i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ADDR-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP3]], align 16
+; ADDR-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @store.v4i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; ORIGINS-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP3]], align 16
+; ORIGINS-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16
+; ORIGINS-NEXT: ret void
+;
+ store <4 x i32> zeroinitializer, ptr %p
+ ret void
+}
+
+define void @store.v8i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @store.v8i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[TMP3]], align 32
+; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @store.v8i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ADDR-NEXT: store <8 x i32> zeroinitializer, ptr [[TMP3]], align 32
+; ADDR-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @store.v8i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; ORIGINS-NEXT: store <8 x i32> zeroinitializer, ptr [[TMP3]], align 32
+; ORIGINS-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32
+; ORIGINS-NEXT: ret void
+;
+ store <8 x i32> zeroinitializer, ptr %p
+ ret void
+}
+
+define void @store.v16i32(ptr %p) sanitize_address {
+; CHECK-LABEL: @store.v16i32(
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[TMP3]], align 64
+; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64
+; CHECK-NEXT: ret void
+;
+; ADDR-LABEL: @store.v16i32(
+; ADDR-NEXT: call void @llvm.donothing()
+; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr [[TMP3]], align 64
+; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64
+; ADDR-NEXT: ret void
+;
+; ORIGINS-LABEL: @store.v16i32(
+; ORIGINS-NEXT: call void @llvm.donothing()
+; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
+; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr [[TMP3]], align 64
+; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64
+; ORIGINS-NEXT: ret void
+;
+ store <16 x i32> zeroinitializer, ptr %p
+ ret void
+}
+
+
More information about the llvm-commits
mailing list