[PATCH] D146037: [RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation

[Alex Bradbury via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG084e4138930d: [RISCV] Fix regression due to interaction of MachineOutliner and… (authored by asb).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146037/new/

https://reviews.llvm.org/D146037

Files:
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll


Index: llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
===================================================================
--- llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
+++ llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
@@ -6,8 +6,6 @@
 ; register copy, which is at risk of being removed by MachineCopyPropagation
 ; if it can't see that the copy is used. At the time of writing this test
 ; case, MCP will remove the copy if it is run after the machine outliner.
-; FIXME: Ensure machine copy propagation is run before the machine outliner so
-; the copy in the outlined function isn't erroneously removed.
 
 define signext i32 @nge(i32 signext %a, i32 signext %b) nounwind {
 entry:
@@ -196,4 +194,5 @@
 ; RV64I-NEXT:    lui s0, 524288
 ; RV64I-NEXT:    addiw s0, s0, -1
 ; RV64I-NEXT:    lui a0, 524288
+; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    jr t0
Index: llvm/test/CodeGen/RISCV/O3-pipeline.ll
===================================================================
--- llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -166,6 +166,7 @@
 ; CHECK-NEXT:       Implement the 'patchable-function' attribute
 ; CHECK-NEXT:       Branch relaxation pass
 ; CHECK-NEXT:       RISCV Make Compressible
+; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       Contiguously Lay Out Funclets
 ; CHECK-NEXT:       StackMap Liveness Analysis
 ; CHECK-NEXT:       Live DEBUG_VALUE analysis
@@ -176,7 +177,6 @@
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       Stack Frame Layout Analysis
 ; CHECK-NEXT:       RISCV pseudo instruction expansion pass
-; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       RISCV atomic pseudo instruction expansion pass
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -337,16 +337,19 @@
 void RISCVPassConfig::addPreEmitPass() {
   addPass(&BranchRelaxationPassID);
   addPass(createRISCVMakeCompressibleOptPass());
+
+  // TODO: It would potentially be better to schedule copy propagation after
+  // expanding pseudos (in addPreEmitPass2). However, performing copy
+  // propagation after the machine outliner (which runs after addPreEmitPass)
+  // currently leads to incorrect code-gen, where copies to registers within
+  // outlined functions are removed erroneously.
+  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
+    addPass(createMachineCopyPropagationPass(true));
 }
 
 void RISCVPassConfig::addPreEmitPass2() {
   addPass(createRISCVExpandPseudoPass());
 
-  // Do the copy propagation after expanding pseudos because we may produce some
-  // MVs when expanding.
-  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
-    addPass(createMachineCopyPropagationPass(true));
-
   // Schedule the expansion of AMOs at the last possible moment, avoiding the
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.


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