[PATCH] D145779: [BOLT][NFC] Improve performance of MCPlusBuilder::initAliases

[Rafael Auler via Phabricator via llvm-commits]

rafauler added inline comments.


================
Comment at: bolt/lib/Core/MCPlusBuilder.cpp:468
   for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I)
-    Worklist.push(I);
-  while (!Worklist.empty()) {
-    MCPhysReg I = Worklist.front();
-    Worklist.pop();
     for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI)
       SmallerAliasMap[I] |= SmallerAliasMap[*SI];
----------------
X86 has registers with subregs, which in turn has their own subregs. e.g. RAX -> EAX -> AX -> AH, AL

I'm curious whether the subreg iterator here is returning the transitive list of all sub regs of a register? e.g. would it return AL as a subreg of RAX?  That's what the old code was computing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145779/new/

https://reviews.llvm.org/D145779