[PATCH] D143361: [RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 13 16:41:21 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp:57
+bool RISCVInsertNTLHInsts::runOnMachineFunction(MachineFunction &MF) {
+ bool Changed = false;
+ TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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Move the declaration and assignment of `Changed` to line 64, right before the loop.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp:71
+ DebugLoc DL = MBBI.getDebugLoc();
+ if (ST.hasStdExtC() && ST.enableRVCHintInstrs())
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoCNTLALL));
----------------
This should be hasStdExtCOrZca()
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1251
+ if (ST.hasStdExtZihintntl() && MMO->isNonTemporal()) {
+ if (ST.hasStdExtC() && ST.enableRVCHintInstrs()) {
+ if (isCompressibleInst(MI, STI))
----------------
COrZca
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td:1
+//RISCVInstrInfoZihintntl.td - RISC-V 'Zihintntl' instructions -*- tablegen -*-//
+//
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This line exceeds 80 characters
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td:14
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 4, isCodeGenOnly = 1 in {
+ def PseudoNTLALL : Pseudo<(outs), (ins), [], "ntl.all">,
----------------
Doesn't the Pseudo class already imply isCodeGenOnly = 1?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143361/new/
https://reviews.llvm.org/D143361
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