[PATCH] D145465: [BOLT][NFC] Return instruction list from createInstrIncMemory
Amir Ayupov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 13 12:57:01 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rG223ec28da44f: [BOLT][NFC] Return instruction list from createInstrIncMemory (authored by Amir).
Changed prior to commit:
https://reviews.llvm.org/D145465?vs=502912&id=504819#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D145465/new/
https://reviews.llvm.org/D145465
Files:
bolt/include/bolt/Core/MCPlusBuilder.h
bolt/lib/Passes/Instrumentation.cpp
bolt/lib/Target/X86/X86MCPlusBuilder.cpp
Index: bolt/lib/Target/X86/X86MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -3030,11 +3030,12 @@
Inst.clear();
}
- void createInstrIncMemory(InstructionListType &Instrs, const MCSymbol *Target,
- MCContext *Ctx, bool IsLeaf) const override {
+ InstructionListType createInstrIncMemory(const MCSymbol *Target,
+ MCContext *Ctx,
+ bool IsLeaf) const override {
+ InstructionListType Instrs(IsLeaf ? 13 : 11);
unsigned int I = 0;
- Instrs.resize(IsLeaf ? 13 : 11);
// Don't clobber application red zone (ABI dependent)
if (IsLeaf)
createStackPointerIncrement(Instrs[I++], 128,
@@ -3061,6 +3062,7 @@
if (IsLeaf)
createStackPointerDecrement(Instrs[I], 128,
/*NoFlagsClobber=*/true);
+ return Instrs;
}
void createSwap(MCInst &Inst, MCPhysReg Source, MCPhysReg MemBaseReg,
Index: bolt/lib/Passes/Instrumentation.cpp
===================================================================
--- bolt/lib/Passes/Instrumentation.cpp
+++ bolt/lib/Passes/Instrumentation.cpp
@@ -174,12 +174,9 @@
InstructionListType
Instrumentation::createInstrumentationSnippet(BinaryContext &BC, bool IsLeaf) {
auto L = BC.scopeLock();
- MCSymbol *Label;
- Label = BC.Ctx->createNamedTempSymbol("InstrEntry");
+ MCSymbol *Label = BC.Ctx->createNamedTempSymbol("InstrEntry");
Summary->Counters.emplace_back(Label);
- InstructionListType CounterInstrs;
- BC.MIB->createInstrIncMemory(CounterInstrs, Label, &*BC.Ctx, IsLeaf);
- return CounterInstrs;
+ return BC.MIB->createInstrIncMemory(Label, BC.Ctx.get(), IsLeaf);
}
// Helper instruction sequence insertion function
@@ -231,8 +228,9 @@
BinaryBasicBlock &FromBB, uint32_t From, BinaryFunction &ToFunc,
BinaryBasicBlock *TargetBB, uint32_t ToOffset, bool IsLeaf, bool IsInvoke,
FunctionDescription *FuncDesc, uint32_t FromNodeID, uint32_t ToNodeID) {
+ BinaryContext &BC = FromFunction.getBinaryContext();
{
- auto L = FromFunction.getBinaryContext().scopeLock();
+ auto L = BC.scopeLock();
bool Created = true;
if (!TargetBB)
Created = createCallDescription(*FuncDesc, FromFunction, From, FromNodeID,
@@ -245,10 +243,8 @@
return false;
}
- InstructionListType CounterInstrs =
- createInstrumentationSnippet(FromFunction.getBinaryContext(), IsLeaf);
+ InstructionListType CounterInstrs = createInstrumentationSnippet(BC, IsLeaf);
- BinaryContext &BC = FromFunction.getBinaryContext();
const MCInst &Inst = *Iter;
if (BC.MIB->isCall(Inst)) {
// This code handles both
Index: bolt/include/bolt/Core/MCPlusBuilder.h
===================================================================
--- bolt/include/bolt/Core/MCPlusBuilder.h
+++ bolt/include/bolt/Core/MCPlusBuilder.h
@@ -450,10 +450,11 @@
virtual MCPhysReg getX86R11() const { llvm_unreachable("not implemented"); }
/// Create increment contents of target by 1 for Instrumentation
- virtual void createInstrIncMemory(InstructionListType &Instrs,
- const MCSymbol *Target, MCContext *Ctx,
- bool IsLeaf) const {
+ virtual InstructionListType createInstrIncMemory(const MCSymbol *Target,
+ MCContext *Ctx,
+ bool IsLeaf) const {
llvm_unreachable("not implemented");
+ return InstructionListType();
}
/// Return a register number that is guaranteed to not match with
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