[llvm] dde08c9 - [AArchExpandPseudo] Preserve instruction debug number in expansions

[Felipe de Azevedo Piovezan via llvm-commits]

Author: Felipe de Azevedo Piovezan
Date: 2023-03-13T15:29:15-04:00
New Revision: dde08c9c4856726136b670af6def50d108f3bfc4

URL: https://github.com/llvm/llvm-project/commit/dde08c9c4856726136b670af6def50d108f3bfc4
DIFF: https://github.com/llvm/llvm-project/commit/dde08c9c4856726136b670af6def50d108f3bfc4.diff

LOG: [AArchExpandPseudo] Preserve instruction debug number in expansions

This is an initial attempt at preserving debug information in the pseudo
instruction expansion of the AArch backend. In particular, we preserve
the instruction number required by the InstrRef implementation of live
debug values.

There are many other expansions that need to be considered, but the ones
addressed in this commit should be extremely common, as they handle most
arithmetic and logical instructions.

Differential Revision: https://reviews.llvm.org/D145943

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 26d59acf60e7..a413c924c862 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1177,6 +1177,8 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
         .add(MI.getOperand(2))
         .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     transferImpOps(MI, MIB1, MIB1);
+    if (auto DebugNumber = MI.peekDebugInstrNum())
+      NewMI->setDebugInstrNum(DebugNumber);
     MI.eraseFromParent();
     return true;
   }

diff  --git a/llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir b/llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
index b09e3b266528..c4a97649801d 100644
--- a/llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
+++ b/llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
@@ -3,8 +3,8 @@
 ---
 # CHECK-LABEL:  name: test
 # CHECK-LABEL:  bb.0:
-# CHECK:          $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv
-# CHECK-NEXT:     $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv
+# CHECK:          $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv, debug-instr-number 1
+# CHECK-NEXT:     $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv, debug-instr-number 2
 # CHECK-NEXT:     RET undef $lr
 #
 name:            test
@@ -14,8 +14,8 @@ body:             |
   bb.0:
     liveins: $w5, $w6, $x2, $x3
 
-    renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv
-    renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv
+    renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv, debug-instr-number 1
+    renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv, debug-instr-number 2
     RET_ReallyLR
 
 ...