[PATCH] D145972: [BOLT][NFC] Provide default impl for MIB methods that are only overridden on X86

Amir Ayupov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 13 11:36:18 PDT 2023


Amir created this revision.
Amir added a reviewer: bolt.
Herald added a reviewer: rafauler.
Herald added subscribers: treapster, ayermolo.
Herald added a reviewer: maksfb.
Herald added a project: All.
Amir requested review of this revision.
Herald added subscribers: llvm-commits, yota9.
Herald added a project: LLVM.

Simplifies D145687 <https://reviews.llvm.org/D145687>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145972

Files:
  bolt/include/bolt/Core/MCPlusBuilder.h
  bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp


Index: bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -45,8 +45,6 @@
                                  *AArch64ExprB.getSubExpr(), Comp);
   }
 
-  bool hasEVEXEncoding(const MCInst &) const override { return false; }
-
   bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override {
     return false;
   }
@@ -1091,14 +1089,6 @@
     return true;
   }
 
-  bool isMoveMem2Reg(const MCInst &Inst) const override { return false; }
-
-  bool isLeave(const MCInst &Inst) const override { return false; }
-
-  bool isPop(const MCInst &Inst) const override { return false; }
-
-  bool isPrefix(const MCInst &Inst) const override { return false; }
-
   bool createReturn(MCInst &Inst) const override {
     Inst.setOpcode(AArch64::RET);
     Inst.clear();
Index: bolt/include/bolt/Core/MCPlusBuilder.h
===================================================================
--- bolt/include/bolt/Core/MCPlusBuilder.h
+++ bolt/include/bolt/Core/MCPlusBuilder.h
@@ -497,12 +497,10 @@
   }
 
   virtual bool isPrefix(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
     return false;
   }
 
   virtual bool isRep(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
     return false;
   }
 
@@ -516,7 +514,6 @@
   }
 
   virtual bool isPop(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
     return false;
   }
 
@@ -556,7 +553,6 @@
   }
 
   virtual bool isLeave(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
     return false;
   }
 
@@ -575,7 +571,6 @@
   }
 
   virtual bool isMoveMem2Reg(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
     return false;
   }
 
@@ -862,7 +857,6 @@
 
   /// Return true if the instruction is encoded using EVEX (AVX-512).
   virtual bool hasEVEXEncoding(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
     return false;
   }
 


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