[llvm] c7d844e - [DAG] Use ISD::isBitwiseLogicOp in AND/OR/XOR checks. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 13 06:39:28 PDT 2023
Author: Simon Pilgrim
Date: 2023-03-13T13:39:02Z
New Revision: c7d844ea0fae1e135028755de071a8c63ab6431a
URL: https://github.com/llvm/llvm-project/commit/c7d844ea0fae1e135028755de071a8c63ab6431a
DIFF: https://github.com/llvm/llvm-project/commit/c7d844ea0fae1e135028755de071a8c63ab6431a.diff
LOG: [DAG] Use ISD::isBitwiseLogicOp in AND/OR/XOR checks. NFCI.
There's additional cases we can cleanup (mainly in target code), but this tries to cleanup generic code and PPC which had an equivalent helper.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9d54ba34c5a58..e362fcb6dc958 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5591,8 +5591,7 @@ SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
EVT VT = N0.getValueType();
unsigned LogicOpcode = N->getOpcode();
unsigned HandOpcode = N0.getOpcode();
- assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||
- LogicOpcode == ISD::XOR) && "Expected logic opcode");
+ assert(ISD::isBitwiseLogicOp(LogicOpcode) && "Expected logic opcode");
assert(HandOpcode == N1.getOpcode() && "Bad input!");
// Bail early if none of these transforms apply.
@@ -6560,9 +6559,8 @@ static SDValue foldAndToUsubsat(SDNode *N, SelectionDAG &DAG) {
static SDValue foldLogicOfShifts(SDNode *N, SDValue LogicOp, SDValue ShiftOp,
SelectionDAG &DAG) {
unsigned LogicOpcode = N->getOpcode();
- assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||
- LogicOpcode == ISD::XOR)
- && "Expected bitwise logic operation");
+ assert(ISD::isBitwiseLogicOp(LogicOpcode) &&
+ "Expected bitwise logic operation");
if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse())
return SDValue();
@@ -6609,8 +6607,8 @@ static SDValue foldLogicOfShifts(SDNode *N, SDValue LogicOp, SDValue ShiftOp,
static SDValue foldLogicTreeOfShifts(SDNode *N, SDValue LeftHand,
SDValue RightHand, SelectionDAG &DAG) {
unsigned LogicOpcode = N->getOpcode();
- assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||
- LogicOpcode == ISD::XOR));
+ assert(ISD::isBitwiseLogicOp(LogicOpcode) &&
+ "Expected bitwise logic operation");
if (LeftHand.getOpcode() != LogicOpcode ||
RightHand.getOpcode() != LogicOpcode)
return SDValue();
@@ -12503,8 +12501,7 @@ SDValue DAGCombiner::CombineZExtLogicopShiftLoad(SDNode *N) {
// and/or/xor
SDValue N0 = N->getOperand(0);
- if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
- N0.getOpcode() == ISD::XOR) ||
+ if (!ISD::isBitwiseLogicOp(N0.getOpcode()) ||
N0.getOperand(1).getOpcode() != ISD::Constant ||
(LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT)))
return SDValue();
@@ -12984,8 +12981,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// fold (sext (and/or/xor (load x), cst)) ->
// (and/or/xor (sextload x), (sext cst))
- if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
- N0.getOpcode() == ISD::XOR) &&
+ if (ISD::isBitwiseLogicOp(N0.getOpcode()) &&
isa<LoadSDNode>(N0.getOperand(0)) &&
N0.getOperand(1).getOpcode() == ISD::Constant &&
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
@@ -13287,8 +13283,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
// (and/or/xor (zextload x), (zext cst))
// Unless (and (load x) cst) will match as a zextload already and has
// additional users.
- if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
- N0.getOpcode() == ISD::XOR) &&
+ if (ISD::isBitwiseLogicOp(N0.getOpcode()) &&
isa<LoadSDNode>(N0.getOperand(0)) &&
N0.getOperand(1).getOpcode() == ISD::Constant &&
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 2f2ae6e29855b..5f7e3fe8b1665 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -454,8 +454,7 @@ bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
if (!TLI.isTypeLegal(VT)) {
// MVT::i1 is special. Allow AND, OR, or XOR because they
// don't require additional zeroing, which makes them easy.
- if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
- ISDOpcode == ISD::XOR))
+ if (VT == MVT::i1 && ISD::isBitwiseLogicOp(ISDOpcode))
VT = TLI.getTypeToTransformTo(I->getContext(), VT);
else
return false;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 2c450a332ef4a..e5220aec4f388 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -2846,9 +2846,6 @@ class IntegerCompareEliminator {
}
};
-static bool isLogicOp(unsigned Opc) {
- return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
-}
// The obvious case for wanting to keep the value in a GPR. Namely, the
// result of the comparison is actually needed in a GPR.
SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
@@ -2858,7 +2855,7 @@ SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
SDValue WideRes;
// If we are zero-extending the result of a logical operation on i1
// values, we can keep the values in GPRs.
- if (isLogicOp(N->getOperand(0).getOpcode()) &&
+ if (ISD::isBitwiseLogicOp(N->getOperand(0).getOpcode()) &&
N->getOperand(0).getValueType() == MVT::i1 &&
N->getOpcode() == ISD::ZERO_EXTEND)
WideRes = computeLogicOpInGPR(N->getOperand(0));
@@ -2894,7 +2891,7 @@ SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
if (N->getValueType(0) != MVT::i1)
return nullptr;
- assert(isLogicOp(N->getOpcode()) &&
+ assert(ISD::isBitwiseLogicOp(N->getOpcode()) &&
"Expected a logic operation on setcc results.");
SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0));
if (!LoweredLogical)
@@ -2974,7 +2971,7 @@ SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
// There is also a special case that is handled (namely a complement operation
// achieved with xor %a, -1).
SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) {
- assert(isLogicOp(LogicOp.getOpcode()) &&
+ assert(ISD::isBitwiseLogicOp(LogicOp.getOpcode()) &&
"Can only handle logic operations here.");
assert(LogicOp.getValueType() == MVT::i1 &&
"Can only handle logic operations on i1 values here.");
@@ -2999,7 +2996,7 @@ SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) {
PPC::RLDICL, dl, InVT, InputOp,
S->getI64Imm(0, dl),
S->getI64Imm(63, dl)), 0);
- } else if (isLogicOp(OperandOpcode))
+ } else if (ISD::isBitwiseLogicOp(OperandOpcode))
return computeLogicOpInGPR(Operand);
return SDValue();
};
@@ -3888,7 +3885,7 @@ static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
CompareUse->getOpcode() != ISD::SELECT &&
- !isLogicOp(CompareUse->getOpcode())) {
+ !ISD::isBitwiseLogicOp(CompareUse->getOpcode())) {
OmittedForNonExtendUses++;
return false;
}
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