[PATCH] D145650: [X86][WIP] Create extra prolog/epilog for stack realignment
LuoYuanke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 13 05:07:28 PDT 2023
LuoYuanke added inline comments.
================
Comment at: llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir:31
; CHECK-LABEL: name: test
- ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4456458 /* regdef:GR64 */, def $rsi, 4456458 /* regdef:GR64 */, def dead $rdi,
- INLINEASM &foo, 0, 4456458, def $rsi, 4456458, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
+ ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4521994 /* regdef:GR64 */, def $rsi, 4521994 /* regdef:GR64 */, def dead $rdi,
+ INLINEASM &foo, 0, 4521994, def $rsi, 4521994, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
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GR64 register class ID is changed from 67 to 68. Since register class is encoded in the flag, this test case need to be updated.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D145650/new/
https://reviews.llvm.org/D145650
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