[llvm] c0c4c72 - [RISCV] Return false for unsupported VTs in isFPImmLegal.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 12 23:34:36 PDT 2023
Author: Craig Topper
Date: 2023-03-12T23:34:13-07:00
New Revision: c0c4c725e98c7339d8dbc8eec2a773d26f87929b
URL: https://github.com/llvm/llvm-project/commit/c0c4c725e98c7339d8dbc8eec2a773d26f87929b
DIFF: https://github.com/llvm/llvm-project/commit/c0c4c725e98c7339d8dbc8eec2a773d26f87929b.diff
LOG: [RISCV] Return false for unsupported VTs in isFPImmLegal.
I don't have a test case that fails for this, but it seemed like
we should only handle legal types. The callers I looked at in
DAGCombine either check the type is legal or don't even call
isFPImmLegal unless LegalOperations is true.
Written in a slightly odd way because switches on EVT require
an additional isSimple check so an if/else chain is easier. Used a bool
to shorten the code instead of having multiple ifs and returns.
AArch64 uses a similarish structure.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 95009ca9cd14..c8a9d02d7062 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1558,11 +1558,15 @@ bool RISCVTargetLowering::isLegalZfaFPImm(const APFloat &Imm, EVT VT) const {
bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
- if (VT == MVT::f16 && !Subtarget.hasStdExtZfhOrZfhmin())
- return false;
- if (VT == MVT::f32 && !Subtarget.hasStdExtF())
- return false;
- if (VT == MVT::f64 && !Subtarget.hasStdExtD())
+ bool IsLegalVT = false;
+ if (VT == MVT::f16)
+ IsLegalVT = Subtarget.hasStdExtZfhOrZfhmin();
+ else if (VT == MVT::f32)
+ IsLegalVT = Subtarget.hasStdExtF();
+ else if (VT == MVT::f64)
+ IsLegalVT = Subtarget.hasStdExtD();
+
+ if (!IsLegalVT)
return false;
if (isLegalZfaFPImm(Imm, VT))
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