[llvm] 00eef4f - [SelectionDAG] Fix mismatched truncate when combine BUILD_VECTOR with EXTRACT_SUBVECTOR
Jun Ma via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 12 18:00:10 PDT 2023
Author: Jun Ma
Date: 2023-03-13T08:59:52+08:00
New Revision: 00eef4f7c384456e0df8f855b99eab384a213c23
URL: https://github.com/llvm/llvm-project/commit/00eef4f7c384456e0df8f855b99eab384a213c23
DIFF: https://github.com/llvm/llvm-project/commit/00eef4f7c384456e0df8f855b99eab384a213c23.diff
LOG: [SelectionDAG] Fix mismatched truncate when combine BUILD_VECTOR with EXTRACT_SUBVECTOR
Just use correct type for truncation. Fixes PR59625
Differential Revision: https://reviews.llvm.org/D145757
Added:
llvm/test/CodeGen/WebAssembly/pr59625.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 245be4aef7cd..4ab490d6ff59 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -23525,7 +23525,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
if (NumElems == 1) {
SDValue Src = V->getOperand(IdxVal);
if (EltVT != Src.getValueType())
- Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), InVT, Src);
+ Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Src);
return DAG.getBitcast(NVT, Src);
}
diff --git a/llvm/test/CodeGen/WebAssembly/pr59625.ll b/llvm/test/CodeGen/WebAssembly/pr59625.ll
new file mode 100644
index 000000000000..4c3d9226e934
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/pr59625.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=wasm32-- -mattr=+simd128 | FileCheck --check-prefix=CHECK %s
+; RUN: llc < %s -mtriple=wasm64-- -mattr=+simd128 | FileCheck --check-prefix=CHECK %s
+
+define <1 x i16> @f(<1 x i16> %0) {
+; CHECK-LABEL: f:
+; CHECK: .functype f (v128) -> (v128)
+; CHECK-NEXT: # %bb.0: # %BB
+; CHECK-NEXT: v128.const 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: # fallthrough-return
+BB:
+ %B2 = srem <1 x i16> %0, %0
+ br label %BB1
+
+BB1: ; preds = %BB
+ %B = urem <1 x i16> %B2, <i16 3>
+ ret <1 x i16> %B
+}
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