[llvm] 4058249 - [RISCV] Add overrides of isLoadFromStackSlot/isStoreFromStackSlot signatures that don't have MemBytes.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-12T09:52:49-07:00
New Revision: 40582493f06375f0b8199626cdd690aab608f5ae

URL: https://github.com/llvm/llvm-project/commit/40582493f06375f0b8199626cdd690aab608f5ae
DIFF: https://github.com/llvm/llvm-project/commit/40582493f06375f0b8199626cdd690aab608f5ae.diff

LOG: [RISCV] Add overrides of isLoadFromStackSlot/isStoreFromStackSlot signatures that don't have MemBytes.

D145471 added overrides of the other signature to return MemBytes,
but shouldn't have removed these overrides.

These signatures will now call the MemBytes signature and ignore
the MemBytes. This matches X86.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 3bb50c08bee0..08f1c9ffb738 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -77,6 +77,12 @@ MCInst RISCVInstrInfo::getNop() const {
       .addImm(0);
 }
 
+unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+                                             int &FrameIndex) const {
+  unsigned Dummy;
+  return isLoadFromStackSlot(MI, FrameIndex, Dummy);
+}
+
 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
                                              int &FrameIndex,
                                              unsigned &MemBytes) const {
@@ -112,6 +118,12 @@ unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   return 0;
 }
 
+unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+                                            int &FrameIndex) const {
+  unsigned Dummy;
+  return isStoreToStackSlot(MI, FrameIndex, Dummy);
+}
+
 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                             int &FrameIndex,
                                             unsigned &MemBytes) const {

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index f0f5fd14922f..cc84e9c07d0d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -49,8 +49,12 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   MCInst getNop() const override;
   const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
 
+  unsigned isLoadFromStackSlot(const MachineInstr &MI,
+                               int &FrameIndex) const override;
   unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
                                unsigned &MemBytes) const override;
+  unsigned isStoreToStackSlot(const MachineInstr &MI,
+                              int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
                               unsigned &MemBytes) const override;