[PATCH] D145867: [X86][FP16] Optimize FMAXNUM/FMINNUM into SMAX/SMIN for FP16 emulation under fast math

[Phoebe Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:53165
   EVT VT = N->getValueType(0);
-  if (Subtarget.useSoftFloat() || isSoftFP16(VT, Subtarget))
+  if (Subtarget.useSoftFloat() || isSoftFP16(VT, Subtarget)) {
+    if (DAG.getTarget().Options.NoNaNsFPMath || N->getFlags().hasNoNaNs()) {
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RKSimon wrote:
> We might need to improve soft float test coverage?
Good catch! I didn't intend to support soft float. And IIRC, we have problems in supporting soft float. So bail it out.


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Comment at: llvm/test/CodeGen/X86/half.ll:1368
+; CHECK-LIBCALL-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK-LIBCALL-NEXT:    retq
+;
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RKSimon wrote:
> It seems a shame to scalarize this when we're already on the FPU, and we have pminsw/pmaxsw since SSE2
Good point! We can vectorize it first, though we still need to improve the `f16` extract.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145867/new/

https://reviews.llvm.org/D145867