[PATCH] D143708: [RISCV] Support emulated TLS

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/emutls.ll:7
+
+; Make sure that TLS symbols are emitted in expected order.
+
----------------
I still don’t see what the point of this comment is


================
Comment at: llvm/test/CodeGen/RISCV/emutls.ll:10
+ at external_x = external thread_local global i32, align 8
+ at external_y = thread_local global i8 7, align 2
+ at internal_y = internal thread_local global i64 9, align 16
----------------
This isn’t external?


================
Comment at: llvm/test/CodeGen/RISCV/emutls.ll:17
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
----------------
Use nounwind to avoid these


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143708/new/

https://reviews.llvm.org/D143708