[llvm] b7021a3 - [X86] Add regcall CC test case for base pointer register.
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 10 19:06:42 PST 2023
Author: Luo, Yuanke
Date: 2023-03-11T11:06:27+08:00
New Revision: b7021a3bed7be2205ee6ad2f0154495da37e506c
URL: https://github.com/llvm/llvm-project/commit/b7021a3bed7be2205ee6ad2f0154495da37e506c
DIFF: https://github.com/llvm/llvm-project/commit/b7021a3bed7be2205ee6ad2f0154495da37e506c.diff
LOG: [X86] Add regcall CC test case for base pointer register.
Added:
Modified:
llvm/test/CodeGen/X86/i386-baseptr.ll
llvm/test/CodeGen/X86/x86-64-baseptr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/i386-baseptr.ll b/llvm/test/CodeGen/X86/i386-baseptr.ll
index 448658d93ee7..498f2e0f6af6 100644
--- a/llvm/test/CodeGen/X86/i386-baseptr.ll
+++ b/llvm/test/CodeGen/X86/i386-baseptr.ll
@@ -72,6 +72,54 @@ entry:
ret void
}
+define x86_regcallcc void @clobber_baseptr_argptr(i32 %param1, i32 %param2, i32 %param3, i32 %param4, i32 %param5, i32 %param6) #0 {
+; CHECK-LABEL: clobber_baseptr_argptr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushl %ebp
+; CHECK-NEXT: movl %esp, %ebp
+; CHECK-NEXT: pushl %ebx
+; CHECK-NEXT: andl $-128, %esp
+; CHECK-NEXT: subl $128, %esp
+; CHECK-NEXT: movl %esp, %esi
+; CHECK-NEXT: movl 8(%ebp), %edi
+; CHECK-NEXT: calll helper at PLT
+; CHECK-NEXT: movl %esp, %ecx
+; CHECK-NEXT: leal 31(,%eax,4), %eax
+; CHECK-NEXT: andl $-32, %eax
+; CHECK-NEXT: movl %ecx, %edx
+; CHECK-NEXT: subl %eax, %edx
+; CHECK-NEXT: movl %edx, %esp
+; CHECK-NEXT: negl %eax
+; CHECK-NEXT: movl $405, %esi # imm = 0x195
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl $405, %ebx # imm = 0x195
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl $8, %edx
+; CHECK-NEXT: #APP
+; CHECK-NEXT: movl %edx, (%esi)
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl %edi, (%ecx,%eax)
+; CHECK-NEXT: leal -4(%ebp), %esp
+; CHECK-NEXT: popl %ebx
+; CHECK-NEXT: popl %ebp
+; CHECK-NEXT: retl
+entry:
+ %k = call i32 @helper()
+ %a = alloca i32, align 128
+ %b = alloca i32, i32 %k, align 4
+ ; clobber base pointer register
+ tail call void asm sideeffect "nop", "{si}"(i32 405)
+ ; clobber argument pointer register
+ tail call void asm sideeffect "nop", "{bx}"(i32 405)
+ call void asm sideeffect "movl $0, $1", "r,*m"(i32 8, ptr elementtype(i32) %a)
+ store i32 %param6, ptr %b, align 4
+ ret void
+}
+
attributes #0 = { nounwind "frame-pointer"="all"}
!llvm.module.flags = !{!0}
!0 = !{i32 2, !"override-stack-alignment", i32 32}
diff --git a/llvm/test/CodeGen/X86/x86-64-baseptr.ll b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
index decf1f0e437e..47f83c8e8706 100644
--- a/llvm/test/CodeGen/X86/x86-64-baseptr.ll
+++ b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
@@ -137,6 +137,121 @@ entry:
ret void
}
+define x86_regcallcc void @clobber_baseptr_argptr(i32 %param1, i32 %param2, i32 %param3, i32 %param4, i32 %param5, i32 %param6, i32 %param7, i32 %param8, i32 %param9, i32 %param10, i32 %param11, i32 %param12) #0 {
+; CHECK-LABEL: clobber_baseptr_argptr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: andq $-128, %rsp
+; CHECK-NEXT: subq $256, %rsp # imm = 0x100
+; CHECK-NEXT: movaps %xmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm10, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movaps %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: movq %rsp, %rbx
+; CHECK-NEXT: movl 16(%rbp), %r14d
+; CHECK-NEXT: callq helper at PLT
+; CHECK-NEXT: movq %rsp, %rcx
+; CHECK-NEXT: movl %eax, %eax
+; CHECK-NEXT: leaq 31(,%rax,4), %rax
+; CHECK-NEXT: andq $-32, %rax
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: subq %rax, %rdx
+; CHECK-NEXT: movq %rdx, %rsp
+; CHECK-NEXT: negq %rax
+; CHECK-NEXT: movl $405, %ebx # imm = 0x195
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl $8, %edx
+; CHECK-NEXT: #APP
+; CHECK-NEXT: movl %edx, (%rbx)
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl %r14d, (%rcx,%rax)
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm12 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm13 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm14 # 16-byte Reload
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload
+; CHECK-NEXT: leaq -8(%rbp), %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+;
+; X32ABI-LABEL: clobber_baseptr_argptr:
+; X32ABI: # %bb.0: # %entry
+; X32ABI-NEXT: pushq %rbp
+; X32ABI-NEXT: movl %esp, %ebp
+; X32ABI-NEXT: pushq %rbx
+; X32ABI-NEXT: andl $-128, %esp
+; X32ABI-NEXT: subl $256, %esp # imm = 0x100
+; X32ABI-NEXT: movaps %xmm15, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm14, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm13, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm12, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm11, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm10, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm9, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movaps %xmm8, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X32ABI-NEXT: movl %esp, %ebx
+; X32ABI-NEXT: movl 16(%ebp), %r14d
+; X32ABI-NEXT: callq helper at PLT
+; X32ABI-NEXT: # kill: def $eax killed $eax def $rax
+; X32ABI-NEXT: leal 31(,%rax,4), %eax
+; X32ABI-NEXT: andl $-32, %eax
+; X32ABI-NEXT: movl %esp, %ecx
+; X32ABI-NEXT: movl %ecx, %edx
+; X32ABI-NEXT: subl %eax, %edx
+; X32ABI-NEXT: negl %eax
+; X32ABI-NEXT: movl %edx, %esp
+; X32ABI-NEXT: movl $405, %ebx # imm = 0x195
+; X32ABI-NEXT: #APP
+; X32ABI-NEXT: nop
+; X32ABI-NEXT: #NO_APP
+; X32ABI-NEXT: #APP
+; X32ABI-NEXT: nop
+; X32ABI-NEXT: #NO_APP
+; X32ABI-NEXT: movl $8, %edx
+; X32ABI-NEXT: #APP
+; X32ABI-NEXT: movl %edx, (%ebx)
+; X32ABI-NEXT: #NO_APP
+; X32ABI-NEXT: movl %r14d, (%ecx,%eax)
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm8 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm9 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm10 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm11 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm12 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm13 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm14 # 16-byte Reload
+; X32ABI-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm15 # 16-byte Reload
+; X32ABI-NEXT: leal -8(%ebp), %esp
+; X32ABI-NEXT: popq %rbx
+; X32ABI-NEXT: popq %rbp
+; X32ABI-NEXT: retq
+entry:
+ %k = call i32 @helper()
+ %a = alloca i32, align 128
+ %b = alloca i32, i32 %k, align 4
+ ; clobber base pointer register
+ tail call void asm sideeffect "nop", "{bx}"(i32 405)
+ ; clobber argument pointer register
+ tail call void asm sideeffect "nop", "~{bx},~{r10},~{r11}"()
+ call void asm sideeffect "movl $0, $1", "r,*m"(i32 8, ptr elementtype(i32) %a)
+ store i32 %param12, ptr %b, align 4
+ ret void
+}
+
attributes #0 = { nounwind "frame-pointer"="all"}
!llvm.module.flags = !{!0}
!0 = !{i32 2, !"override-stack-alignment", i32 32}
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