[PATCH] D143335: [AMDGPU] Use instruction order in machine function to process workList of moveToVALU
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 10 16:31:17 PST 2023
arsenm added inline comments.
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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:69
+ return {};
+ ReversePostOrderTraversal<const MachineBasicBlock *> RPOT(&*MF->begin());
+ std::vector<const MachineBasicBlock *> RPOList;
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It doesn't make sense to me to construct RPO to create a list like this. The whole iteration would just work in RPO
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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:75-77
+// Compare machine instructions based on their order
+// in the machine function. Returns true if first instruction
+// occurs before second instruction in the machine function.
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This should be implied by the iteration order, shouldn't need to sort
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143335/new/
https://reviews.llvm.org/D143335
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