[llvm] d84e971 - [SLP][NFC]Add a test with multilevel dependency between buildvector

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2023-03-10T10:33:03-08:00
New Revision: d84e971f48bc2ebab11bd01dd6bb9e8441419dcb

URL: https://github.com/llvm/llvm-project/commit/d84e971f48bc2ebab11bd01dd6bb9e8441419dcb
DIFF: https://github.com/llvm/llvm-project/commit/d84e971f48bc2ebab11bd01dd6bb9e8441419dcb.diff

LOG: [SLP][NFC]Add a test with multilevel dependency between buildvector
nodes, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll
new file mode 100644
index 000000000000..3221b5283aca
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64 < %s | FileCheck %s
+
+define double @test() {
+; CHECK-LABEL: define double @test() {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load double, ptr null, align 8
+; CHECK-NEXT:    br label [[COND_TRUE:%.*]]
+; CHECK:       cond.true:
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
+; CHECK-NEXT:    [[TMP6:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP0]], i32 1
+; CHECK-NEXT:    [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], zeroinitializer
+; CHECK-NEXT:    [[TMP9:%.*]] = fsub <2 x double> [[TMP8]], zeroinitializer
+; CHECK-NEXT:    [[TMP10:%.*]] = fmul <2 x double> [[TMP8]], zeroinitializer
+; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP12:%.*]] = fadd <2 x double> zeroinitializer, [[TMP11]]
+; CHECK-NEXT:    [[TMP13:%.*]] = fmul <2 x double> zeroinitializer, [[TMP11]]
+; CHECK-NEXT:    [[TMP14:%.*]] = shufflevector <2 x double> [[TMP12]], <2 x double> [[TMP13]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP15:%.*]] = fsub <2 x double> [[TMP14]], [[TMP2]]
+; CHECK-NEXT:    [[TMP16:%.*]] = fadd <2 x double> [[TMP14]], [[TMP2]]
+; CHECK-NEXT:    [[TMP17:%.*]] = shufflevector <2 x double> [[TMP15]], <2 x double> [[TMP16]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP18:%.*]] = fsub <2 x double> [[TMP17]], zeroinitializer
+; CHECK-NEXT:    [[TMP19:%.*]] = fmul <2 x double> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP20:%.*]] = fmul <2 x double> zeroinitializer, [[TMP19]]
+; CHECK-NEXT:    [[TMP21:%.*]] = fadd <2 x double> [[TMP20]], [[TMP18]]
+; CHECK-NEXT:    [[TMP22:%.*]] = fsub <2 x double> [[TMP21]], zeroinitializer
+; CHECK-NEXT:    [[TMP23:%.*]] = fmul <2 x double> [[TMP6]], zeroinitializer
+; CHECK-NEXT:    [[TMP24:%.*]] = fmul <2 x double> zeroinitializer, [[TMP23]]
+; CHECK-NEXT:    [[TMP25:%.*]] = fadd <2 x double> [[TMP24]], [[TMP22]]
+; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <2 x double> [[TMP25]], i32 0
+; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <2 x double> [[TMP25]], i32 1
+; CHECK-NEXT:    [[ADD29:%.*]] = fadd double [[TMP26]], [[TMP27]]
+; CHECK-NEXT:    ret double [[ADD29]]
+;
+entry:
+  %0 = load double, ptr null, align 8
+  br label %cond.true
+
+cond.true:
+  %mul13 = fmul double %0, 0.000000e+00
+  %mul14 = fmul double %0, 0.000000e+00
+  %mul15 = fmul double %mul14, 0.000000e+00
+  %mul16 = fmul double 0.000000e+00, %mul15
+  %add17 = fadd double %mul13, %mul16
+  %sub18 = fsub double %add17, 0.000000e+00
+  %mul19 = fmul double %0, 0.000000e+00
+  %mul20 = fmul double %mul19, 0.000000e+00
+  %mul21 = fmul double %mul20, 0.000000e+00
+  %add22 = fadd double %sub18, %mul21
+  %sub23 = fsub double %add22, 0.000000e+00
+  %mul24 = fmul double %0, 0.000000e+00
+  %mul25 = fmul double %mul24, 0.000000e+00
+  %mul26 = fmul double 0.000000e+00, %mul25
+  %add27 = fadd double %mul26, %sub23
+  %mul = fmul double 0.000000e+00, 0.000000e+00
+  %mul1 = fmul double %mul, 0.000000e+00
+  %sub = fsub double %mul1, 0.000000e+00
+  %add = fadd double 0.000000e+00, %sub
+  %sub2 = fsub double %add, %mul
+  %sub3 = fsub double %sub2, 0.000000e+00
+  %mul4 = fmul double %0, 0.000000e+00
+  %mul5 = fmul double %mul4, 0.000000e+00
+  %mul6 = fmul double 0.000000e+00, %mul5
+  %add7 = fadd double %mul6, %sub3
+  %sub8 = fsub double %add7, 0.000000e+00
+  %mul9 = fmul double %0, 0.000000e+00
+  %mul10 = fmul double %mul9, 0.000000e+00
+  %mul11 = fmul double 0.000000e+00, %mul10
+  %add12 = fadd double %mul11, %sub8
+  %add29 = fadd double %add12, %add27
+  ret double %add29
+}