[PATCH] D145649: [RISCV] Enable Zfa fli.h instruction in MC layer with Zfhmin and Zvfh.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGed8d75ef2619: [RISCV] Enable Zfa fli.h instruction in MC layer with Zfhmin and Zvfh. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D145649?vs=503614&id=504157#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145649/new/

https://reviews.llvm.org/D145649

Files:
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
  llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s


Index: llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+experimental-zvfh -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+experimental-zvfh -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+experimental-zvfh < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+experimental-zvfh -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+experimental-zvfh < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+experimental-zvfh -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# This test makes sure fli.h is supported with Zvfh.
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, -1.0
+# CHECK-ASM: encoding: [0xd3,0x00,0x10,0xf4]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point), 'Zfh' (Half-Precision Floating-Point) or 'Zvfh' (Vector Half-Precision Floating-Point){{$}}
+fli.h ft1, -1.0
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -135,10 +135,11 @@
                     Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 } // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
 
-let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
+let Predicates = [HasStdExtZfa, HasStdExtZfhOrZvfh] in
 def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, OPC_OP_FP, (outs FPR16:$rd),
             (ins loadfp16imm:$imm), "fli.h", "$rd, $imm">;
 
+let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
 def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, /*Commutable*/ 1>;
 def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, /*Commutable*/ 1>;
 
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -424,6 +424,12 @@
                        "'Zvfh' (Vector Half-Precision Floating-Point)",
                        [FeatureStdExtZve32f]>;
 
+def HasStdExtZfhOrZvfh
+    : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
+                AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
+                                   "'Zfh' (Half-Precision Floating-Point) or "
+                                   "'Zvfh' (Vector Half-Precision Floating-Point)">;
+
 def FeatureStdExtZicbom
     : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
                        "'Zicbom' (Cache-Block Management Instructions)">;


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