[llvm] 2eada45 - [AMDGPU][MachineVerifier] Fix vdata reg count for MIMG d16

[Mirko Brkusanin via llvm-commits]

Author: Mirko Brkusanin
Date: 2023-03-10T14:47:49+01:00
New Revision: 2eada459c7651d851e427b4062bc2940c2bb4b1e

URL: https://github.com/llvm/llvm-project/commit/2eada459c7651d851e427b4062bc2940c2bb4b1e
DIFF: https://github.com/llvm/llvm-project/commit/2eada459c7651d851e427b4062bc2940c2bb4b1e.diff

LOG: [AMDGPU][MachineVerifier] Fix vdata reg count for MIMG d16

Differential Revision: https://reviews.llvm.org/D145785

Added: 
    llvm/test/CodeGen/AMDGPU/verify-image.mir

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    llvm/test/CodeGen/AMDGPU/verify-image-partial-nsa.mir


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d75abd8fed750..a1d13cc491eb7 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4346,7 +4346,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
 
       // Adjust for packed 16 bit values
       if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
-        RegCount >>= 1;
+        RegCount = divideCeil(RegCount, 2);
 
       // Adjust if using LWE or TFE
       if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
@@ -4359,7 +4359,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
         const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
         uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
         if (RegCount > DstSize) {
-          ErrInfo = "MIMG instruction returns too many registers for dst "
+          ErrInfo = "Image instruction returns too many registers for dst "
                     "register class";
           return false;
         }

diff  --git a/llvm/test/CodeGen/AMDGPU/verify-image-partial-nsa.mir b/llvm/test/CodeGen/AMDGPU/verify-image.mir
similarity index 79%
rename from llvm/test/CodeGen/AMDGPU/verify-image-partial-nsa.mir
rename to llvm/test/CodeGen/AMDGPU/verify-image.mir
index df275390349a6..62de9ab05918c 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-image-partial-nsa.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-image.mir
@@ -1,7 +1,7 @@
-# RUN: not --crash llc -march=amdgcn -mcpu=gfx11 -run-pass=machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s
+# RUN: not --crash llc -march=amdgcn -mcpu=gfx1100 -run-pass=machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s
 
 ---
-name: image_sample_d_v1v9_nsa_partial
+name: image_verify
 body:             |
   bb.0:
     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
@@ -23,6 +23,11 @@ body:             |
     ; GFX11-ERR: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 is not a VReg_160 register.
 
     renamable $vgpr11 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
+
+    ; GFX11-ERR: *** Bad machine code: Image instruction returns too many registers for dst register class ***
+    ; GFX11-ERR: - instruction: renamable $vgpr12 = IMAGE_SAMPLE_V1_V1_gfx11 renamable $vgpr0, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 7, 0, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load (s128), addrspace 7)
+
+    renamable $vgpr12 = IMAGE_SAMPLE_V1_V1_gfx11 renamable $vgpr0, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 7, 0, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load (s128), addrspace 7)
 ...
 
 # GFX11-ERR-NOT: *** Bad machine code