[PATCH] D145650: [X86] Create extra prolog/epilog for stack realignment

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp:76
+  case CallingConv::X86_RegCall:
+    return STI.is64Bit() ? X86::RBX : X86::EBX;
+  default:
----------------
pengfei wrote:
> Are we replacing RBX with RBX on 64-bits?
Good catch, we may have to need virtual register since inline assembly may clobber any physical register.


================
Comment at: llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp:79
+    if (STI.is64Bit()) {
+      return X86::R10;
+    } else {
----------------
pengfei wrote:
> Why `R10`? Do you want `R11`, according to ABI
> ```
> %r10 temporary register, used for passing a function’s static chain pointer No
> %r11 temporary register                                                     No
> ```
Both R10 and R11 should be OK, but we should use virtual register.


================
Comment at: llvm/test/CodeGen/X86/swifttail-realign.ll:9
 ; CHECK-LABEL: caller:
+; CHECK: andq $-32, %rsp
 ; CHECK: subq $16, %rsp
----------------
pengfei wrote:
> No sure if it's correct. I assume the old code used `rsp` to access `%ptr` but it is intentionally omitted.
> It must be wrong if the new code still use `rsp` because it is not aligned to 32 now.
There is alignment instruction `andq    $-32, %rax` in both the old code and new code. 

```
        movq    %rsp, %rax
        addq    $15, %rdi
        andq    $-16, %rdi
        subq    %rdi, %rax
        andq    $-32, %rax
        movq    %rax, %rsp
        movq    var at GOTPCREL(%rip), %rcx
        movq    %rax, (%rcx)
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145650/new/

https://reviews.llvm.org/D145650