[PATCH] D145785: [AMDGPU][MachineVerifier] Fix vdata reg count for MIMG d16
Mirko Brkusanin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 10 04:46:36 PST 2023
mbrkusanin created this revision.
mbrkusanin added reviewers: foad, arsenm.
mbrkusanin added a project: LLVM.
Herald added subscribers: kosarev, StephenFan, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: All.
mbrkusanin requested review of this revision.
Herald added a subscriber: wdng.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D145785
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/verify-image-partial-nsa.mir
llvm/test/CodeGen/AMDGPU/verify-image.mir
Index: llvm/test/CodeGen/AMDGPU/verify-image.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/verify-image.mir
+++ llvm/test/CodeGen/AMDGPU/verify-image.mir
@@ -1,7 +1,7 @@
-# RUN: not --crash llc -march=amdgcn -mcpu=gfx11 -run-pass=machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s
+# RUN: not --crash llc -march=amdgcn -mcpu=gfx1100 -run-pass=machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s
---
-name: image_sample_d_v1v9_nsa_partial
+name: image_verify
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
@@ -23,6 +23,11 @@
; GFX11-ERR: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 is not a VReg_160 register.
renamable $vgpr11 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
+
+ ; GFX11-ERR: *** Bad machine code: Image instruction returns too many registers for dst register class ***
+ ; GFX11-ERR: - instruction: renamable $vgpr12 = IMAGE_SAMPLE_V1_V1_gfx11 renamable $vgpr0, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 7, 0, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load (s128), addrspace 7)
+
+ renamable $vgpr12 = IMAGE_SAMPLE_V1_V1_gfx11 renamable $vgpr0, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 7, 0, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load (s128), addrspace 7)
...
# GFX11-ERR-NOT: *** Bad machine code
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4346,7 +4346,7 @@
// Adjust for packed 16 bit values
if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
- RegCount >>= 1;
+ RegCount = (RegCount + 1) >> 1;
// Adjust if using LWE or TFE
if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
@@ -4359,7 +4359,7 @@
const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
if (RegCount > DstSize) {
- ErrInfo = "MIMG instruction returns too many registers for dst "
+ ErrInfo = "Image instruction returns too many registers for dst "
"register class";
return false;
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D145785.504101.patch
Type: text/x-patch
Size: 2843 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230310/a0e2c446/attachment.bin>
More information about the llvm-commits
mailing list