[PATCH] D145155: [RISCV] Enable interleaved access vectorization

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 503775.
luke added a comment.

Model wide load and shuffle


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145155/new/

https://reviews.llvm.org/D145155

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-zve32x.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
  llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll

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