[llvm] 3ae310d - Fix VGPR + offset Scratch offset folding
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 9 01:55:09 PST 2023
Author: Petar Avramovic
Date: 2023-03-09T10:52:44+01:00
New Revision: 3ae310d0ae3452c7384736c7f8542ee3d1e0f4fd
URL: https://github.com/llvm/llvm-project/commit/3ae310d0ae3452c7384736c7f8542ee3d1e0f4fd
DIFF: https://github.com/llvm/llvm-project/commit/3ae310d0ae3452c7384736c7f8542ee3d1e0f4fd.diff
LOG: Fix VGPR + offset Scratch offset folding
Values in VGPR register are treated as unsigned by hardware.
When value in 32-bit VGPR base can be negative calculate offset using
32-bit add instruction, otherwise use vgpr base(unsigned) + offset.
Does not affect case where whole offset comes from VGPR register
(immediate offset is 0).
LoopStrengthReduce.cpp changes offsets to negative and in some
iterations value in VGPR register could be negative.
Differential Revision: https://reviews.llvm.org/D144956
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/memory_clause.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 54cb8e59a8498..1bee1c315053b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -1537,7 +1537,8 @@ bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl(SDNode *N, SDValue Addr,
if (Subtarget->hasFlatInstOffsets() && !CanHaveFlatSegmentOffsetBug) {
SDValue N0, N1;
- if (isBaseWithConstantOffset64(Addr, N0, N1)) {
+ if (isBaseWithConstantOffset64(Addr, N0, N1) &&
+ isFlatScratchBaseLegal(N0, FlatVariant)) {
int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
const SIInstrInfo *TII = Subtarget->getInstrInfo();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 088843779a893..cefbcf69bb987 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -3847,7 +3847,7 @@ AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root,
int64_t ConstOffset;
std::tie(PtrBase, ConstOffset) =
getPtrBaseWithConstantOffset(Root.getReg(), *MRI);
- if (ConstOffset == 0)
+ if (ConstOffset == 0 || !isFlatScratchBaseLegal(PtrBase, FlatVariant))
return Default;
unsigned AddrSpace = (*MI->memoperands_begin())->getAddrSpace();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
index cf01ff4f90926..ff4515e371434 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
@@ -416,6 +416,7 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) {
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_add_u32_e32 v3, 8, v0
; FLATSCR-NEXT: v_writelane_b32 v41, s0, 0
; FLATSCR-NEXT: s_add_u32 s0, s32, 8
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
@@ -423,30 +424,36 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) {
; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s32
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:8
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v3, off
+; FLATSCR-NEXT: v_add_u32_e32 v3, 16, v0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:16
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v3, off
; FLATSCR-NEXT: s_add_u32 s0, s32, 16
+; FLATSCR-NEXT: v_add_u32_e32 v3, 24, v0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:24
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v3, off
; FLATSCR-NEXT: s_add_u32 s0, s32, 24
+; FLATSCR-NEXT: v_add_u32_e32 v3, 32, v0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:32
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v3, off
; FLATSCR-NEXT: s_add_u32 s0, s32, 32
+; FLATSCR-NEXT: v_add_u32_e32 v3, 40, v0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:40
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v3, off
; FLATSCR-NEXT: s_add_u32 s0, s32, 40
+; FLATSCR-NEXT: v_add_u32_e32 v3, 48, v0
+; FLATSCR-NEXT: v_add_u32_e32 v0, 56, v0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:48
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v3, off
; FLATSCR-NEXT: s_add_u32 s0, s32, 48
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
-; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], v0, off offset:56
+; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_byval at rel32@hi+12
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
index 1369b02d87fe1..858ccf7aa3501 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
@@ -90,15 +90,17 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: v_add_u32_e32 v1, 4, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 15
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v2, off
+; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 4
+; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7c
+; GFX9-NEXT: v_add3_u32 v0, v2, v0, v1
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -110,13 +112,14 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-NEXT: v_mov_b32_e32 v2, 15
+; GFX10-NEXT: v_mov_b32_e32 v2, 0x7c
+; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v1, 4, v1
-; GFX10-NEXT: scratch_store_dword v0, v2, off
+; GFX10-NEXT: v_add3_u32 v1, 4, v1, v2
+; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
@@ -227,8 +230,9 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX9-LABEL: private_ptr_foo:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX9-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX9-NEXT: scratch_store_dword v0, v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -236,16 +240,18 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX10-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: private_ptr_foo:
; GFX940: ; %bb.0:
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX940-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX940-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX940-NEXT: scratch_store_dword v0, v1, off
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
@@ -253,8 +259,8 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:4
+; GFX11-NEXT: v_dual_mov_b32 v1, 0x41200000 :: v_dual_add_nc_u32 v0, 4, v0
+; GFX11-NEXT: scratch_store_b32 v0, v1, off
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr inbounds float, ptr addrspace(5) %arg, i32 1
@@ -363,14 +369,16 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: v_add_u32_e32 v1, 0x104, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 15
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v2, off
+; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x104
+; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, 0x104, v0
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7c
+; GFX9-NEXT: v_add3_u32 v0, v2, v0, v1
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -382,15 +390,16 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-NEXT: v_mov_b32_e32 v2, 15
-; GFX10-NEXT: scratch_load_dword v3, off, off offset:4 glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v2, 0x7c
+; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x104, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x104, v1
-; GFX10-NEXT: scratch_store_dword v0, v2, off
+; GFX10-NEXT: v_add3_u32 v1, 0x104, v1, v2
+; GFX10-NEXT: scratch_load_dword v2, off, off offset:4 glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
@@ -623,14 +632,16 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: v_add_u32_e32 v1, 0x4004, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 15
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v2, off
+; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x4004
+; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, 0x4004, v0
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x7c
+; GFX9-NEXT: v_add3_u32 v0, v2, v0, v1
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -642,15 +653,16 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-NEXT: v_mov_b32_e32 v2, 15
-; GFX10-NEXT: scratch_load_dword v3, off, off offset:4 glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v2, 0x7c
+; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x4004, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x4004, v1
-; GFX10-NEXT: scratch_store_dword v0, v2, off
+; GFX10-NEXT: v_add3_u32 v1, 0x4004, v1, v2
+; GFX10-NEXT: scratch_load_dword v2, off, off offset:4 glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
@@ -935,14 +947,16 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, 4
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x400
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_add_lshl_u32 v0, s0, v0, 2
-; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
-; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024
+; GFX9-NEXT: v_add3_u32 v0, v1, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, 15
+; GFX9-NEXT: scratch_store_dword v0, v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 glc
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -953,13 +967,14 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v1, 15
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x400
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_add_lshl_u32 v0, s0, v0, 2
-; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0
-; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024
+; GFX10-NEXT: v_add3_u32 v0, 4, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 15
+; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
index 2fe38a64c8d86..4bf6b6a623d82 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
@@ -270,7 +270,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], 2047, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 2047
@@ -361,7 +363,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], 2048, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2048, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 2048
@@ -405,7 +409,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], -2047, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2047, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 -2047
@@ -449,7 +455,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], -2048, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2048, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 -2048
@@ -491,7 +499,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], 4095, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 4095
@@ -581,7 +591,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], -4095, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4095, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 -4095
@@ -625,7 +637,9 @@ body: |
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[COPY]], -4096, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4096, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 -4096
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
index 9ed5369b1a4d9..854739a594751 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
@@ -750,7 +750,10 @@ body: |
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec
- ; GFX11-NEXT: SCRATCH_STORE_DWORD [[COPY]], [[V_LSHRREV_B32_e64_]], 4095, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 5)
+ ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_LSHRREV_B32_e64_]], [[COPY1]], 0, implicit $exec
+ ; GFX11-NEXT: SCRATCH_STORE_DWORD [[COPY]], [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 5)
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
%2:sgpr(s32) = G_CONSTANT i32 4095
@@ -793,7 +796,9 @@ body: |
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec
- ; GFX11-NEXT: SCRATCH_STORE_DWORD [[COPY]], [[V_LSHRREV_B32_e64_]], 4095, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 5)
+ ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_LSHRREV_B32_e64_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX11-NEXT: SCRATCH_STORE_DWORD [[COPY]], [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 5)
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
%2:vgpr(s32) = G_CONSTANT i32 4095
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index c3684e24dc2aa..35794c9737860 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -734,11 +734,11 @@ define <2 x i16> @chain_hi_to_lo_private_other_dep(ptr addrspace(5) %ptr) {
; FLATSCR: ; %bb.0: ; %bb
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: scratch_load_short_d16_hi v1, v0, off
+; FLATSCR-NEXT: v_add_u32_e32 v2, 2, v0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; FLATSCR-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
-; FLATSCR-NEXT: scratch_load_short_d16 v1, v0, off offset:2
+; FLATSCR-NEXT: v_pk_sub_u16 v0, v1, -12 op_sel_hi:[1,0]
+; FLATSCR-NEXT: scratch_load_short_d16 v0, v2, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; FLATSCR-NEXT: v_mov_b32_e32 v0, v1
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
;
; GFX10_DEFAULT-LABEL: chain_hi_to_lo_private_other_dep:
@@ -758,11 +758,11 @@ define <2 x i16> @chain_hi_to_lo_private_other_dep(ptr addrspace(5) %ptr) {
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; FLATSCR_GFX10-NEXT: scratch_load_short_d16_hi v1, v0, off
+; FLATSCR_GFX10-NEXT: v_add_nc_u32_e32 v2, 2, v0
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
-; FLATSCR_GFX10-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
-; FLATSCR_GFX10-NEXT: scratch_load_short_d16 v1, v0, off offset:2
+; FLATSCR_GFX10-NEXT: v_pk_sub_u16 v0, v1, -12 op_sel_hi:[1,0]
+; FLATSCR_GFX10-NEXT: scratch_load_short_d16 v0, v2, off
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
-; FLATSCR_GFX10-NEXT: v_mov_b32_e32 v0, v1
; FLATSCR_GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: chain_hi_to_lo_private_other_dep:
@@ -770,11 +770,11 @@ define <2 x i16> @chain_hi_to_lo_private_other_dep(ptr addrspace(5) %ptr) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_d16_hi_b16 v1, v0, off
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 2, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
-; GFX11-NEXT: scratch_load_d16_b16 v1, v0, off offset:2
+; GFX11-NEXT: v_pk_sub_u16 v0, v1, -12 op_sel_hi:[1,0]
+; GFX11-NEXT: scratch_load_d16_b16 v0, v2, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, ptr addrspace(5) %ptr, i64 1
diff --git a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
index 8184764aa352b..596daadd277ba 100644
--- a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
+++ b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
@@ -46,10 +46,11 @@ define i32 @private_load_2xi16_align2(ptr addrspace(5) %p) #0 {
; GFX9-FLASTSCR-LABEL: private_load_2xi16_align2:
; GFX9-FLASTSCR: ; %bb.0:
; GFX9-FLASTSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-FLASTSCR-NEXT: scratch_load_ushort v1, v0, off
-; GFX9-FLASTSCR-NEXT: scratch_load_ushort v2, v0, off offset:2
+; GFX9-FLASTSCR-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX9-FLASTSCR-NEXT: scratch_load_ushort v2, v0, off
+; GFX9-FLASTSCR-NEXT: scratch_load_ushort v3, v1, off
; GFX9-FLASTSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLASTSCR-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX9-FLASTSCR-NEXT: v_lshl_or_b32 v0, v3, 16, v2
; GFX9-FLASTSCR-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: private_load_2xi16_align2:
@@ -67,33 +68,36 @@ define i32 @private_load_2xi16_align2(ptr addrspace(5) %p) #0 {
; GFX10-FLASTSCR: ; %bb.0:
; GFX10-FLASTSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLASTSCR-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-FLASTSCR-NEXT: v_add_nc_u32_e32 v1, 2, v0
; GFX10-FLASTSCR-NEXT: s_clause 0x1
-; GFX10-FLASTSCR-NEXT: scratch_load_ushort v1, v0, off
-; GFX10-FLASTSCR-NEXT: scratch_load_ushort v2, v0, off offset:2
+; GFX10-FLASTSCR-NEXT: scratch_load_ushort v2, v0, off
+; GFX10-FLASTSCR-NEXT: scratch_load_ushort v3, v1, off
; GFX10-FLASTSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLASTSCR-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX10-FLASTSCR-NEXT: v_lshl_or_b32 v0, v3, 16, v2
; GFX10-FLASTSCR-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: private_load_2xi16_align2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 2, v0
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: scratch_load_u16 v1, v0, off
-; GFX11-NEXT: scratch_load_u16 v0, v0, off offset:2
+; GFX11-NEXT: scratch_load_u16 v0, v0, off
+; GFX11-NEXT: scratch_load_u16 v1, v1, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLASTSCR-LABEL: private_load_2xi16_align2:
; GFX11-FLASTSCR: ; %bb.0:
; GFX11-FLASTSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLASTSCR-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FLASTSCR-NEXT: v_add_nc_u32_e32 v1, 2, v0
; GFX11-FLASTSCR-NEXT: s_clause 0x1
-; GFX11-FLASTSCR-NEXT: scratch_load_u16 v1, v0, off
-; GFX11-FLASTSCR-NEXT: scratch_load_u16 v0, v0, off offset:2
+; GFX11-FLASTSCR-NEXT: scratch_load_u16 v0, v0, off
+; GFX11-FLASTSCR-NEXT: scratch_load_u16 v1, v1, off
; GFX11-FLASTSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FLASTSCR-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FLASTSCR-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FLASTSCR-NEXT: s_setpc_b64 s[30:31]
%gep.p = getelementptr i16, ptr addrspace(5) %p, i64 1
%p.0 = load i16, ptr addrspace(5) %p, align 2
@@ -142,10 +146,11 @@ define void @private_store_2xi16_align2(ptr addrspace(5) %p, ptr addrspace(5) %r
; GFX9-FLASTSCR-LABEL: private_store_2xi16_align2:
; GFX9-FLASTSCR: ; %bb.0:
; GFX9-FLASTSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-FLASTSCR-NEXT: v_mov_b32_e32 v0, 1
-; GFX9-FLASTSCR-NEXT: scratch_store_short v1, v0, off
-; GFX9-FLASTSCR-NEXT: v_mov_b32_e32 v0, 2
-; GFX9-FLASTSCR-NEXT: scratch_store_short v1, v0, off offset:2
+; GFX9-FLASTSCR-NEXT: v_mov_b32_e32 v2, 1
+; GFX9-FLASTSCR-NEXT: v_add_u32_e32 v0, 2, v1
+; GFX9-FLASTSCR-NEXT: scratch_store_short v1, v2, off
+; GFX9-FLASTSCR-NEXT: v_mov_b32_e32 v1, 2
+; GFX9-FLASTSCR-NEXT: scratch_store_short v0, v1, off
; GFX9-FLASTSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLASTSCR-NEXT: s_setpc_b64 s[30:31]
;
@@ -165,9 +170,10 @@ define void @private_store_2xi16_align2(ptr addrspace(5) %p, ptr addrspace(5) %r
; GFX10-FLASTSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLASTSCR-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLASTSCR-NEXT: v_mov_b32_e32 v0, 1
-; GFX10-FLASTSCR-NEXT: v_mov_b32_e32 v2, 2
+; GFX10-FLASTSCR-NEXT: v_add_nc_u32_e32 v2, 2, v1
+; GFX10-FLASTSCR-NEXT: v_mov_b32_e32 v3, 2
; GFX10-FLASTSCR-NEXT: scratch_store_short v1, v0, off
-; GFX10-FLASTSCR-NEXT: scratch_store_short v1, v2, off offset:2
+; GFX10-FLASTSCR-NEXT: scratch_store_short v2, v3, off
; GFX10-FLASTSCR-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLASTSCR-NEXT: s_setpc_b64 s[30:31]
;
@@ -175,11 +181,11 @@ define void @private_store_2xi16_align2(ptr addrspace(5) %p, ptr addrspace(5) %r
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 1
-; GFX11-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v3, 2
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 2, v1
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b16 v1, v0, off
-; GFX11-NEXT: scratch_store_b16 v1, v2, off offset:2
+; GFX11-NEXT: scratch_store_b16 v2, v3, off
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -187,11 +193,11 @@ define void @private_store_2xi16_align2(ptr addrspace(5) %p, ptr addrspace(5) %r
; GFX11-FLASTSCR: ; %bb.0:
; GFX11-FLASTSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLASTSCR-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FLASTSCR-NEXT: v_mov_b32_e32 v0, 1
-; GFX11-FLASTSCR-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-FLASTSCR-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v3, 2
+; GFX11-FLASTSCR-NEXT: v_add_nc_u32_e32 v2, 2, v1
; GFX11-FLASTSCR-NEXT: s_clause 0x1
; GFX11-FLASTSCR-NEXT: scratch_store_b16 v1, v0, off
-; GFX11-FLASTSCR-NEXT: scratch_store_b16 v1, v2, off offset:2
+; GFX11-FLASTSCR-NEXT: scratch_store_b16 v2, v3, off
; GFX11-FLASTSCR-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FLASTSCR-NEXT: s_setpc_b64 s[30:31]
%gep.r = getelementptr i16, ptr addrspace(5) %r, i64 1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
index 0cd62c9aeb258..8e2dc728757fd 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
@@ -11,14 +11,16 @@ define amdgpu_ps void @test_scratch_load_i8_zext_v(ptr addrspace(5) %in, ptr %ou
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: scratch_load_ubyte v0, v0, off offset:1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX10-NEXT: scratch_load_ubyte v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i8_zext_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: scratch_load_u8 v0, v0, off offset:1
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX11-NEXT: scratch_load_u8 v0, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -37,14 +39,16 @@ define amdgpu_ps void @test_scratch_load_i8_sext_v(ptr addrspace(5) %in, ptr %ou
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: scratch_load_sbyte v0, v0, off offset:1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX10-NEXT: scratch_load_sbyte v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i8_sext_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: scratch_load_i8 v0, v0, off offset:1
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; GFX11-NEXT: scratch_load_i8 v0, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -63,14 +67,16 @@ define amdgpu_ps void @test_scratch_load_i16_zext_v(ptr addrspace(5) %in, ptr %o
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: scratch_load_ushort v0, v0, off offset:2
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX10-NEXT: scratch_load_ushort v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i16_zext_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: scratch_load_u16 v0, v0, off offset:2
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-NEXT: scratch_load_u16 v0, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -89,14 +95,16 @@ define amdgpu_ps void @test_scratch_load_i16_sext_v(ptr addrspace(5) %in, ptr %o
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: scratch_load_sshort v0, v0, off offset:2
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX10-NEXT: scratch_load_sshort v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i16_sext_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: scratch_load_i16 v0, v0, off offset:2
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-NEXT: scratch_load_i16 v0, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -115,16 +123,17 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_lo_v(ptr addrspace(5) %i
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX10-NEXT: scratch_load_ubyte_d16 v3, v0, off offset:1
+; GFX10-NEXT: scratch_load_ubyte_d16 v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i8_zext_to_d16_lo_v:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX11-NEXT: scratch_load_d16_u8 v3, v0, off offset:1
+; GFX11-NEXT: v_dual_mov_b32 v3, 0xffff0000 :: v_dual_add_nc_u32 v0, 1, v0
+; GFX11-NEXT: scratch_load_d16_u8 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -145,16 +154,17 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_lo_v(ptr addrspace(5) %i
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX10-NEXT: scratch_load_sbyte_d16 v3, v0, off offset:1
+; GFX10-NEXT: scratch_load_sbyte_d16 v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i8_sext_to_d16_lo_v:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX11-NEXT: scratch_load_d16_i8 v3, v0, off offset:1
+; GFX11-NEXT: v_dual_mov_b32 v3, 0xffff0000 :: v_dual_add_nc_u32 v0, 1, v0
+; GFX11-NEXT: scratch_load_d16_i8 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -175,16 +185,17 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_lo_v(ptr addrspace(5) %in, p
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX10-NEXT: scratch_load_short_d16 v3, v0, off offset:2
+; GFX10-NEXT: scratch_load_short_d16 v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i16_to_d16_lo_v:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX11-NEXT: scratch_load_d16_b16 v3, v0, off offset:2
+; GFX11-NEXT: v_dual_mov_b32 v3, 0xffff0000 :: v_dual_add_nc_u32 v0, 2, v0
+; GFX11-NEXT: scratch_load_d16_b16 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -205,16 +216,17 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_v(ptr addrspace(5) %i
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: scratch_load_ubyte_d16_hi v3, v0, off offset:1
+; GFX10-NEXT: scratch_load_ubyte_d16_hi v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i8_zext_to_d16_hi_v:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v3, -1
-; GFX11-NEXT: scratch_load_d16_hi_u8 v3, v0, off offset:1
+; GFX11-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_add_nc_u32 v0, 1, v0
+; GFX11-NEXT: scratch_load_d16_hi_u8 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -235,16 +247,17 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_v(ptr addrspace(5) %i
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: scratch_load_sbyte_d16_hi v3, v0, off offset:1
+; GFX10-NEXT: scratch_load_sbyte_d16_hi v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i8_sext_to_d16_hi_v:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v3, -1
-; GFX11-NEXT: scratch_load_d16_hi_i8 v3, v0, off offset:1
+; GFX11-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_add_nc_u32 v0, 1, v0
+; GFX11-NEXT: scratch_load_d16_hi_i8 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -265,16 +278,17 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_v(ptr addrspace(5) %in, p
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: scratch_load_short_d16_hi v3, v0, off offset:2
+; GFX10-NEXT: scratch_load_short_d16_hi v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_load_i16_to_d16_hi_v:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v3, -1
-; GFX11-NEXT: scratch_load_d16_hi_b16 v3, v0, off offset:2
+; GFX11-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_add_nc_u32 v0, 2, v0
+; GFX11-NEXT: scratch_load_d16_hi_b16 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -295,15 +309,17 @@ define amdgpu_ps void @test_scratch_store_b8_from_d16_hi_v(ptr %in, ptr addrspac
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: flat_load_dword v0, v[0:1]
+; GFX10-NEXT: v_add_nc_u32_e32 v1, 4, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT: scratch_store_byte_d16_hi v2, v0, off offset:4
+; GFX10-NEXT: scratch_store_byte_d16_hi v1, v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_store_b8_from_d16_hi_v:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: flat_load_b32 v0, v[0:1]
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 4, v2
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: scratch_store_d16_hi_b8 v2, v0, off offset:4
+; GFX11-NEXT: scratch_store_d16_hi_b8 v1, v0, off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
bb:
@@ -322,15 +338,17 @@ define amdgpu_ps void @test_scratch_store_b16_from_d16_hi_v(ptr %in, ptr addrspa
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: flat_load_dword v0, v[0:1]
+; GFX10-NEXT: v_add_nc_u32_e32 v1, 2, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT: scratch_store_short_d16_hi v2, v0, off offset:2
+; GFX10-NEXT: scratch_store_short_d16_hi v1, v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_store_b16_from_d16_hi_v:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: flat_load_b32 v0, v[0:1]
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 2, v2
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: scratch_store_d16_hi_b16 v2, v0, off offset:2
+; GFX11-NEXT: scratch_store_d16_hi_b16 v1, v0, off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
bb:
@@ -719,8 +737,9 @@ define amdgpu_ps void @test_scratch_load_i8_zext_svs(ptr addrspace(5) inreg %in,
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX10-NEXT: scratch_load_ubyte v0, v0, off offset:1
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 1
+; GFX10-NEXT: scratch_load_ubyte v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
@@ -749,8 +768,9 @@ define amdgpu_ps void @test_scratch_load_i8_sext_svs(ptr addrspace(5) inreg %in,
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX10-NEXT: scratch_load_sbyte v0, v0, off offset:1
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 1
+; GFX10-NEXT: scratch_load_sbyte v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
@@ -779,8 +799,9 @@ define amdgpu_ps void @test_scratch_load_i16_zext_svs(ptr addrspace(5) inreg %in
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX10-NEXT: scratch_load_ushort v0, v0, off offset:2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 2
+; GFX10-NEXT: scratch_load_ushort v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
@@ -809,8 +830,9 @@ define amdgpu_ps void @test_scratch_load_i16_sext_svs(ptr addrspace(5) inreg %in
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX10-NEXT: scratch_load_sshort v0, v0, off offset:2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 2
+; GFX10-NEXT: scratch_load_sshort v0, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v0
; GFX10-NEXT: s_endpgm
@@ -839,9 +861,10 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_lo_svs(ptr addrspace(5)
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX10-NEXT: scratch_load_ubyte_d16 v3, v0, off offset:1
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 1
+; GFX10-NEXT: scratch_load_ubyte_d16 v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
@@ -872,9 +895,10 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_lo_svs(ptr addrspace(5)
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX10-NEXT: scratch_load_sbyte_d16 v3, v0, off offset:1
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 1
+; GFX10-NEXT: scratch_load_sbyte_d16 v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
@@ -905,9 +929,10 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_lo_svs(ptr addrspace(5) inre
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff0000
-; GFX10-NEXT: scratch_load_short_d16 v3, v0, off offset:2
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 2
+; GFX10-NEXT: scratch_load_short_d16 v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
@@ -938,9 +963,10 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_svs(ptr addrspace(5)
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: scratch_load_ubyte_d16_hi v3, v0, off offset:1
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 1
+; GFX10-NEXT: scratch_load_ubyte_d16_hi v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
@@ -971,9 +997,10 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_svs(ptr addrspace(5)
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: scratch_load_sbyte_d16_hi v3, v0, off offset:1
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 1
+; GFX10-NEXT: scratch_load_sbyte_d16_hi v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
@@ -1004,9 +1031,10 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_svs(ptr addrspace(5) inre
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: scratch_load_short_d16_hi v3, v0, off offset:2
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, 2
+; GFX10-NEXT: scratch_load_short_d16_hi v3, v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: flat_store_dword v[1:2], v3
; GFX10-NEXT: s_endpgm
@@ -1037,9 +1065,10 @@ define amdgpu_ps void @test_scratch_store_b8_from_d16_hi_svs(ptr %in, ptr addrsp
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: flat_load_dword v0, v[0:1]
-; GFX10-NEXT: v_lshl_add_u32 v1, v2, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v2
+; GFX10-NEXT: v_add3_u32 v1, s2, v1, 4
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT: scratch_store_byte_d16_hi v1, v0, off offset:4
+; GFX10-NEXT: scratch_store_byte_d16_hi v1, v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_store_b8_from_d16_hi_svs:
@@ -1068,9 +1097,10 @@ define amdgpu_ps void @test_scratch_store_b16_from_d16_hi_svs(ptr %in, ptr addrs
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: flat_load_dword v0, v[0:1]
-; GFX10-NEXT: v_lshl_add_u32 v1, v2, 2, s2
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v2
+; GFX10-NEXT: v_add3_u32 v1, s2, v1, 2
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT: scratch_store_short_d16_hi v1, v0, off offset:2
+; GFX10-NEXT: scratch_store_short_d16_hi v1, v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: test_scratch_store_b16_from_d16_hi_svs:
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
index 4d162e26ebd05..8c53943e37678 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
@@ -31,15 +31,18 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 1
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v3, 2
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v3, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -47,14 +50,17 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 2
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_add_nc_u32 v4, 1, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-SDAG-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-SDAG-NEXT: s_endpgm
@@ -63,14 +69,17 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 2
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_add_nc_u32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -116,13 +125,16 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -132,13 +144,16 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 1, v0
; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_mov_b32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-SDAG-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-SDAG-NEXT: s_endpgm
@@ -149,13 +164,16 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 1, v0
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_mov_b32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -201,13 +219,16 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -233,13 +254,16 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_mov_b32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -282,16 +306,19 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 1
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v3, 2
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v3, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -299,16 +326,18 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 2
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_add_nc_u32 v4, 1, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-SDAG-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-SDAG-NEXT: s_endpgm
@@ -317,16 +346,18 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 2
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_add_nc_u32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -374,13 +405,16 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -393,11 +427,15 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_or_b32_e32 v4, 1, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-SDAG-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-SDAG-NEXT: s_endpgm
@@ -411,11 +449,15 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -463,13 +505,16 @@ define amdgpu_kernel void @soff2_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -500,11 +545,15 @@ define amdgpu_kernel void @soff2_voff4(i32 %soff) {
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -547,34 +596,39 @@ define amdgpu_kernel void @soff4_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 1
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v3, 2
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v3, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff4_voff1:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v4, 4
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 2
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SDAG-NEXT: v_add3_u32 v2, 4, s0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add3_u32 v1, 4, s0, v0
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
-; GFX11-SDAG-NEXT: scratch_store_b8 v2, v1, off offset:1 dlc
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v4, 1, v1
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v1, 2, v1
+; GFX11-SDAG-NEXT: scratch_store_b8 v4, v2, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v2, v3, off offset:2 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v1, v3, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v4, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v5, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-SDAG-NEXT: s_endpgm
@@ -583,16 +637,18 @@ define amdgpu_kernel void @soff4_voff1(i32 %soff) {
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 2
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_add_nc_u32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -640,30 +696,34 @@ define amdgpu_kernel void @soff4_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff4_voff2:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 1, v0
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 2 :: v_dual_lshlrev_b32 v0, 1, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX11-SDAG-NEXT: v_mov_b32_e32 v4, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SDAG-NEXT: v_add3_u32 v3, 4, s0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
-; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 2
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: scratch_store_b8 v3, v2, off offset:2 dlc
+; GFX11-SDAG-NEXT: scratch_store_b8 v1, v3, off dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v4, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
@@ -679,11 +739,15 @@ define amdgpu_kernel void @soff4_voff2(i32 %soff) {
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
@@ -731,13 +795,16 @@ define amdgpu_kernel void @soff4_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX940-GISEL-NEXT: v_add3_u32 v0, v1, s0, v0
-; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 1, v0
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
+; GFX940-GISEL-NEXT: v_mov_b32_e32 v2, 2
+; GFX940-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX940-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
+; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
@@ -768,11 +835,15 @@ define amdgpu_kernel void @soff4_voff4(i32 %soff) {
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_add3_u32 v0, 4, s0, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v5, 2, v0
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:2 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
index 0cc45f28fc501..fa15ba45613fd 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
@@ -638,10 +638,11 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: v_add_u32_e32 v1, 4, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-NEXT: v_sub_u32_e32 v0, 4, v0
; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_sub_u32_e32 v0, 4, v0
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -653,22 +654,24 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, 15
-; GFX10-NEXT: v_add_nc_u32_e32 v1, 4, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, 4, v0
-; GFX10-NEXT: scratch_store_dword v1, v2, off
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, 4, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX10-NEXT: scratch_store_dword v0, v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: store_load_vindex_kernel:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, 4, v0
-; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:4 dlc
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, 4, v0
+; GFX11-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_add_nc_u32 v1, 0x7c, v1
+; GFX11-NEXT: scratch_store_b32 v0, v2, off offset:4 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-NEXT: scratch_load_b32 v0, v1, off glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_endpgm
;
@@ -687,7 +690,8 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_store_dword v1, v2, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-PAL-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
;
@@ -698,7 +702,8 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX940-NEXT: scratch_store_dword v0, v1, off offset:4 sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: v_sub_u32_e32 v0, 4, v0
-; GFX940-NEXT: scratch_load_dword v0, v0, off offset:124 sc0 sc1
+; GFX940-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX940-NEXT: scratch_load_dword v0, v0, off sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_endpgm
;
@@ -715,22 +720,24 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 15
-; GFX10-PAL-NEXT: v_add_nc_u32_e32 v1, 4, v0
-; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, 4, v0
-; GFX10-PAL-NEXT: scratch_store_dword v1, v2, off
+; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v1, 4, v0
+; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, 4, v0
+; GFX10-PAL-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX10-PAL-NEXT: scratch_store_dword v0, v2, off
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX10-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm
;
; GFX11-PAL-LABEL: store_load_vindex_kernel:
; GFX11-PAL: ; %bb.0: ; %bb
-; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-PAL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v2, 4, v0
-; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:4 dlc
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v1, 4, v0
+; GFX11-PAL-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_add_nc_u32 v1, 0x7c, v1
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, off offset:4 dlc
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, off glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX11-PAL-NEXT: s_endpgm
; GCN-LABEL: store_load_vindex_kernel:
@@ -878,8 +885,9 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX9-LABEL: private_ptr_foo:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX9-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX9-NEXT: scratch_store_dword v0, v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -887,8 +895,9 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX10-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -896,24 +905,26 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:4
+; GFX11-NEXT: v_dual_mov_b32 v1, 0x41200000 :: v_dual_add_nc_u32 v0, 4, v0
+; GFX11-NEXT: scratch_store_b32 v0, v1, off
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-PAL-LABEL: private_ptr_foo:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-PAL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: private_ptr_foo:
; GFX940: ; %bb.0:
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX940-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX940-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX940-NEXT: scratch_store_dword v0, v1, off
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
@@ -921,8 +932,9 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX10-PAL: ; %bb.0:
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, 4, v0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:4
+; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
;
@@ -930,8 +942,8 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
; GFX11-PAL: ; %bb.0:
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 0x41200000
-; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:4
+; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 0x41200000 :: v_dual_add_nc_u32 v0, 4, v0
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: private_ptr_foo:
@@ -1683,10 +1695,11 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, 0x104, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-NEXT: v_sub_u32_e32 v0, 0x104, v0
; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_sub_u32_e32 v0, 0x104, v0
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -1700,23 +1713,26 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX10-NEXT: v_mov_b32_e32 v2, 15
; GFX10-NEXT: scratch_load_dword v3, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x104, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0x104, v0
-; GFX10-NEXT: scratch_store_dword v1, v2, off
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0x104, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x104, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX10-NEXT: scratch_store_dword v0, v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: store_load_vindex_small_offset_kernel:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_lshlrev_b32 v0, 2, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0x104, v0
-; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:260 dlc
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0x104, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_add_nc_u32 v1, 0x7c, v1
+; GFX11-NEXT: scratch_store_b32 v0, v2, off offset:260 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-NEXT: scratch_load_b32 v0, v1, off glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_endpgm
;
@@ -1735,10 +1751,11 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_add_u32_e32 v1, 0x104, v0
+; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 0x104, v0
; GFX9-PAL-NEXT: scratch_store_dword v1, v2, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 0x104, v0
-; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-PAL-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
;
@@ -1751,7 +1768,8 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX940-NEXT: scratch_store_dword v0, v1, off offset:260 sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: v_sub_u32_e32 v0, 0x104, v0
-; GFX940-NEXT: scratch_load_dword v0, v0, off offset:124 sc0 sc1
+; GFX940-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX940-NEXT: scratch_load_dword v0, v0, off sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_endpgm
;
@@ -1771,11 +1789,12 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
; GFX1010-PAL-NEXT: scratch_load_dword v3, off, vcc_lo offset:4 glc dlc
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v1, 0x104, v0
-; GFX1010-PAL-NEXT: v_sub_nc_u32_e32 v0, 0x104, v0
-; GFX1010-PAL-NEXT: scratch_store_dword v1, v2, off
+; GFX1010-PAL-NEXT: v_sub_nc_u32_e32 v1, 0x104, v0
+; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v0, 0x104, v0
+; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX1010-PAL-NEXT: scratch_store_dword v0, v2, off
; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1010-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX1010-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1010-PAL-NEXT: s_endpgm
;
@@ -1794,23 +1813,26 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX1030-PAL-NEXT: v_mov_b32_e32 v2, 15
; GFX1030-PAL-NEXT: scratch_load_dword v3, off, off offset:4 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v1, 0x104, v0
-; GFX1030-PAL-NEXT: v_sub_nc_u32_e32 v0, 0x104, v0
-; GFX1030-PAL-NEXT: scratch_store_dword v1, v2, off
+; GFX1030-PAL-NEXT: v_sub_nc_u32_e32 v1, 0x104, v0
+; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v0, 0x104, v0
+; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX1030-PAL-NEXT: scratch_store_dword v0, v2, off
; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1030-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX1030-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
;
; GFX11-PAL-LABEL: store_load_vindex_small_offset_kernel:
; GFX11-PAL: ; %bb.0: ; %bb
-; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_lshlrev_b32 v0, 2, v0
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-PAL-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v2, 0x104, v0
-; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:260 dlc
+; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v1, 0x104, v0
+; GFX11-PAL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-PAL-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_add_nc_u32 v1, 0x7c, v1
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, off offset:260 dlc
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, off glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX11-PAL-NEXT: s_endpgm
bb:
@@ -2739,10 +2761,11 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, 0x4004, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-NEXT: v_sub_u32_e32 v0, 0x4004, v0
; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_sub_u32_e32 v0, 0x4004, v0
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -2756,24 +2779,27 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX10-NEXT: v_mov_b32_e32 v2, 15
; GFX10-NEXT: scratch_load_dword v3, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x4004, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0x4004, v0
-; GFX10-NEXT: scratch_store_dword v1, v2, off
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0x4004, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x4004, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX10-NEXT: scratch_store_dword v0, v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: store_load_vindex_large_offset_kernel:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_lshlrev_b32 v0, 2, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
; GFX11-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0x4004, v0
-; GFX11-NEXT: scratch_store_b32 v0, v1, vcc_lo dlc
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0x4004, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_add_nc_u32 v1, 0x7c, v1
+; GFX11-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-NEXT: scratch_load_b32 v0, v1, off glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_endpgm
;
@@ -2792,10 +2818,11 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_add_u32_e32 v1, 0x4004, v0
+; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 0x4004, v0
; GFX9-PAL-NEXT: scratch_store_dword v1, v2, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 0x4004, v0
-; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
+; GFX9-PAL-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
;
@@ -2809,7 +2836,8 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX940-NEXT: scratch_store_dword v0, v1, vcc_hi sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: v_sub_u32_e32 v0, 0x4004, v0
-; GFX940-NEXT: scratch_load_dword v0, v0, off offset:124 sc0 sc1
+; GFX940-NEXT: v_add_u32_e32 v0, 0x7c, v0
+; GFX940-NEXT: scratch_load_dword v0, v0, off sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_endpgm
;
@@ -2829,11 +2857,12 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
; GFX1010-PAL-NEXT: scratch_load_dword v3, off, vcc_lo offset:4 glc dlc
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v1, 0x4004, v0
-; GFX1010-PAL-NEXT: v_sub_nc_u32_e32 v0, 0x4004, v0
-; GFX1010-PAL-NEXT: scratch_store_dword v1, v2, off
+; GFX1010-PAL-NEXT: v_sub_nc_u32_e32 v1, 0x4004, v0
+; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v0, 0x4004, v0
+; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX1010-PAL-NEXT: scratch_store_dword v0, v2, off
; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1010-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX1010-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1010-PAL-NEXT: s_endpgm
;
@@ -2852,24 +2881,27 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX1030-PAL-NEXT: v_mov_b32_e32 v2, 15
; GFX1030-PAL-NEXT: scratch_load_dword v3, off, off offset:4 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v1, 0x4004, v0
-; GFX1030-PAL-NEXT: v_sub_nc_u32_e32 v0, 0x4004, v0
-; GFX1030-PAL-NEXT: scratch_store_dword v1, v2, off
+; GFX1030-PAL-NEXT: v_sub_nc_u32_e32 v1, 0x4004, v0
+; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v0, 0x4004, v0
+; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v1, 0x7c, v1
+; GFX1030-PAL-NEXT: scratch_store_dword v0, v2, off
; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1030-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
+; GFX1030-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
;
; GFX11-PAL-LABEL: store_load_vindex_large_offset_kernel:
; GFX11-PAL: ; %bb.0: ; %bb
-; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_lshlrev_b32 v0, 2, v0
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
; GFX11-PAL-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v2, 0x4004, v0
-; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, vcc_lo dlc
+; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v1, 0x4004, v0
+; GFX11-PAL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-PAL-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_add_nc_u32 v1, 0x7c, v1
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, off glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX11-PAL-NEXT: s_endpgm
bb:
@@ -3327,16 +3359,17 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX9-LABEL: store_load_vidx_sidx_offset:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
-; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; GFX9-NEXT: v_mov_b32_e32 v1, 4
+; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1
+; GFX9-NEXT: v_add_u32_e32 v0, 0x400, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 15
-; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024
+; GFX9-NEXT: scratch_store_dword v0, v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 glc
+; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -3347,13 +3380,14 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v1, 15
+; GFX10-NEXT: v_mov_b32_e32 v1, 4
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
-; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, 4
-; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024
+; GFX10-NEXT: v_add_lshl_u32 v0, s0, v0, 2
+; GFX10-NEXT: v_add3_u32 v0, v1, v0, 0x400
+; GFX10-NEXT: v_mov_b32_e32 v1, 15
+; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
+; GFX10-NEXT: scratch_load_dword v0, v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
@@ -3380,12 +3414,13 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3
; GFX9-PAL-NEXT: v_add_u32_e32 v0, s0, v0
-; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1
+; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
+; GFX9-PAL-NEXT: v_add_u32_e32 v0, 0x400, v0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15
-; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off offset:1024
+; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 glc
+; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
;
@@ -3413,13 +3448,14 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x0
-; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 4
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, s0, v0
-; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, 4
-; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:1024
+; GFX10-PAL-NEXT: v_add_lshl_u32 v0, s0, v0, 2
+; GFX10-PAL-NEXT: v_add3_u32 v0, v1, v0, 0x400
+; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
+; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm
;
@@ -3874,10 +3910,11 @@ define void @store_load_i32_negative_unaligned(ptr addrspace(5) nocapture %arg)
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 1
-; GFX10-NEXT: scratch_store_byte v0, v1, off offset:-1
+; GFX10-NEXT: scratch_store_byte v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_ubyte v0, v0, off offset:-1 glc dlc
+; GFX10-NEXT: scratch_load_ubyte v0, v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3885,10 +3922,10 @@ define void @store_load_i32_negative_unaligned(ptr addrspace(5) nocapture %arg)
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_mov_b32_e32 v1, 1
-; GFX11-NEXT: scratch_store_b8 v0, v1, off offset:-1 dlc
+; GFX11-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_add_nc_u32 v0, -1, v0
+; GFX11-NEXT: scratch_store_b8 v0, v1, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_load_u8 v0, v0, off offset:-1 glc dlc
+; GFX11-NEXT: scratch_load_u8 v0, v0, off glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -3914,37 +3951,26 @@ define void @store_load_i32_negative_unaligned(ptr addrspace(5) nocapture %arg)
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1010-PAL-LABEL: store_load_i32_negative_unaligned:
-; GFX1010-PAL: ; %bb.0: ; %bb
-; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v0, -1, v0
-; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, 1
-; GFX1010-PAL-NEXT: scratch_store_byte v0, v1, off
-; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1010-PAL-NEXT: scratch_load_ubyte v0, v0, off glc dlc
-; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1010-PAL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-PAL-LABEL: store_load_i32_negative_unaligned:
-; GFX1030-PAL: ; %bb.0: ; %bb
-; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1030-PAL-NEXT: v_mov_b32_e32 v1, 1
-; GFX1030-PAL-NEXT: scratch_store_byte v0, v1, off offset:-1
-; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1030-PAL-NEXT: scratch_load_ubyte v0, v0, off offset:-1 glc dlc
-; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-PAL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-PAL-LABEL: store_load_i32_negative_unaligned:
+; GFX10-PAL: ; %bb.0: ; %bb
+; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 1
+; GFX10-PAL-NEXT: scratch_store_byte v0, v1, off
+; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-PAL-NEXT: scratch_load_ubyte v0, v0, off glc dlc
+; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-PAL-LABEL: store_load_i32_negative_unaligned:
; GFX11-PAL: ; %bb.0: ; %bb
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 1
-; GFX11-PAL-NEXT: scratch_store_b8 v0, v1, off offset:-1 dlc
+; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_add_nc_u32 v0, -1, v0
+; GFX11-PAL-NEXT: scratch_store_b8 v0, v1, off dlc
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: scratch_load_u8 v0, v0, off offset:-1 glc dlc
+; GFX11-PAL-NEXT: scratch_load_u8 v0, v0, off glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
bb:
@@ -3970,11 +3996,11 @@ define void @store_load_i32_large_negative_unaligned(ptr addrspace(5) nocapture
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u32_e32 v0, 0xfffff000, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 0xffffef7f, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 1
-; GFX10-NEXT: scratch_store_byte v0, v1, off offset:-129
+; GFX10-NEXT: scratch_store_byte v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_ubyte v0, v0, off offset:-129 glc dlc
+; GFX10-NEXT: scratch_load_ubyte v0, v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3982,10 +4008,10 @@ define void @store_load_i32_large_negative_unaligned(ptr addrspace(5) nocapture
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_add_nc_u32 v0, 0xfffff000, v0
-; GFX11-NEXT: scratch_store_b8 v0, v1, off offset:-129 dlc
+; GFX11-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_add_nc_u32 v0, 0xffffef7f, v0
+; GFX11-NEXT: scratch_store_b8 v0, v1, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_load_u8 v0, v0, off offset:-129 glc dlc
+; GFX11-NEXT: scratch_load_u8 v0, v0, off glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -4011,38 +4037,26 @@ define void @store_load_i32_large_negative_unaligned(ptr addrspace(5) nocapture
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1010-PAL-LABEL: store_load_i32_large_negative_unaligned:
-; GFX1010-PAL: ; %bb.0: ; %bb
-; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1010-PAL-NEXT: v_add_nc_u32_e32 v0, 0xffffefff, v0
-; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, 1
-; GFX1010-PAL-NEXT: scratch_store_byte v0, v1, off offset:-128
-; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1010-PAL-NEXT: scratch_load_ubyte v0, v0, off offset:-128 glc dlc
-; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1010-PAL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-PAL-LABEL: store_load_i32_large_negative_unaligned:
-; GFX1030-PAL: ; %bb.0: ; %bb
-; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1030-PAL-NEXT: v_add_nc_u32_e32 v0, 0xfffff000, v0
-; GFX1030-PAL-NEXT: v_mov_b32_e32 v1, 1
-; GFX1030-PAL-NEXT: scratch_store_byte v0, v1, off offset:-129
-; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX1030-PAL-NEXT: scratch_load_ubyte v0, v0, off offset:-129 glc dlc
-; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-PAL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-PAL-LABEL: store_load_i32_large_negative_unaligned:
+; GFX10-PAL: ; %bb.0: ; %bb
+; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, 0xffffef7f, v0
+; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 1
+; GFX10-PAL-NEXT: scratch_store_byte v0, v1, off
+; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-PAL-NEXT: scratch_load_ubyte v0, v0, off glc dlc
+; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-PAL-LABEL: store_load_i32_large_negative_unaligned:
; GFX11-PAL: ; %bb.0: ; %bb
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_add_nc_u32 v0, 0xfffff000, v0
-; GFX11-PAL-NEXT: scratch_store_b8 v0, v1, off offset:-129 dlc
+; GFX11-PAL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_add_nc_u32 v0, 0xffffef7f, v0
+; GFX11-PAL-NEXT: scratch_store_b8 v0, v1, off dlc
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-PAL-NEXT: scratch_load_u8 v0, v0, off offset:-129 glc dlc
+; GFX11-PAL-NEXT: scratch_load_u8 v0, v0, off glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/memory_clause.ll b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
index 52dd4afcdca5f..6a1c717a471b4 100644
--- a/llvm/test/CodeGen/AMDGPU/memory_clause.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
@@ -209,20 +209,26 @@ define void @mubuf_clause(ptr addrspace(5) noalias nocapture readonly %arg, ptr
; GCN-SCRATCH-NEXT: v_lshlrev_b32_e32 v2, 4, v31
; GCN-SCRATCH-NEXT: v_and_b32_e32 v18, 0x3ff0, v2
; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v0, v0, v18
+; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v6, 16, v0
+; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v10, 32, v0
+; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v14, 48, v0
; GCN-SCRATCH-NEXT: s_clause 0x3
; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[2:5], v0, off
-; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[6:9], v0, off offset:16
-; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[10:13], v0, off offset:32
-; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[14:17], v0, off offset:48
+; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[6:9], v6, off
+; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[10:13], v10, off
+; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[14:17], v14, off
; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v0, v1, v18
+; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v1, 16, v0
+; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v18, 32, v0
+; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v19, 48, v0
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(3)
; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[2:5], off
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(2)
-; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[6:9], off offset:16
+; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v1, v[6:9], off
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1)
-; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[10:13], off offset:32
+; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v18, v[10:13], off
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0)
-; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[14:17], off offset:48
+; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v19, v[14:17], off
; GCN-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-SCRATCH-NEXT: s_setpc_b64 s[30:31]
bb:
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