[llvm] 006f88d - [RISCV] Remove seemingly unneeded !isPosZero from Zfa code in isFPImmLegal.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-08T22:06:05-08:00
New Revision: 006f88d05dac01f10e63d2487d1da46c3f6ec4f7

URL: https://github.com/llvm/llvm-project/commit/006f88d05dac01f10e63d2487d1da46c3f6ec4f7
DIFF: https://github.com/llvm/llvm-project/commit/006f88d05dac01f10e63d2487d1da46c3f6ec4f7.diff

LOG: [RISCV] Remove seemingly unneeded !isPosZero from Zfa code in isFPImmLegal.

This was added after the patch was approved. I'm not sure why its
there. It doesn't fire in any lit test.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 95254d0e4ee7..8f76fd64095c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -845,8 +845,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (Subtarget->hasStdExtZfa()) {
       if ((VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(APF) != -1) ||
           (VT == MVT::f16 && RISCVLoadFPImm::getLoadFP16Imm(APF) != -1) ||
-          (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(APF) != -1 &&
-           !APF.isPosZero()))
+          (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(APF) != -1))
         break;
     }
 

diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9e22baf71fdd..77e907dd4323 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1536,20 +1536,20 @@ bool RISCVTargetLowering::isOffsetFoldingLegal(
 
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
-  if (Subtarget.hasStdExtZfa()) {
-    if ((VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1) ||
-        (VT == MVT::f16 && RISCVLoadFPImm::getLoadFP16Imm(Imm) != -1) ||
-        (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(Imm) != -1 &&
-         !Imm.isPosZero()))
-      return true;
-  }
-
   if (VT == MVT::f16 && !Subtarget.hasStdExtZfhOrZfhmin())
     return false;
   if (VT == MVT::f32 && !Subtarget.hasStdExtF())
     return false;
   if (VT == MVT::f64 && !Subtarget.hasStdExtD())
     return false;
+
+  if (Subtarget.hasStdExtZfa()) {
+    if ((VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1) ||
+        (VT == MVT::f16 && RISCVLoadFPImm::getLoadFP16Imm(Imm) != -1) ||
+        (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(Imm) != -1))
+      return true;
+  }
+
   // Cannot create a 64 bit floating-point immediate value for rv32.
   if (Subtarget.getXLen() < VT.getScalarSizeInBits()) {
     // td can handle +0.0 or -0.0 already.