[PATCH] D141560: [RISCV][CodeGen] Add codegen pattern for FLI instruction in experimental zfa extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:849
+          (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(APF) != -1 && 
+           !APF.isPosZero()))
+        break;
----------------
Why was this isPosZero check added? It wasn't there when the patch was approved.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141560/new/

https://reviews.llvm.org/D141560