[PATCH] D141247: [GlobalISelEmitter][WIP] handle operand without MVT/class

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/TableGen/GlobalISelEmitter-notypeoperand.ll:1
 // RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
----------------
This should be a .td file, not .ll


================
Comment at: llvm/test/TableGen/GlobalISelEmitter-notypeoperand.ll:7
 // No rule will be added to the match table.
-// CHECK-NOT: GIM-TRY
+// CHECK: GIM-TRY
 
----------------
Should check the actual checks performed, not just there is a matcher


================
Comment at: llvm/utils/TableGen/GlobalISelEmitter.cpp:4594-4595
+
+  // Handle the case where the MVT/register class is omitted in the dest pattern
+  // but MVT exists in the source pattern.
+  if (isa<UnsetInit>(DstChild->getLeafValue())) {
----------------
shchenz wrote:
> arsenm wrote:
> > Where is the type check performed?
> Do you mean check the type for the output pattern's operands? I am not familiar here, do we need type check for the output pattern operands? And the input operands type check should already be handled in previous logic. See the new introduced rule in the new tblgen case `GlobalISelEmitter-notypeoperand.ll`:
> 
> ```
>   constexpr static int64_t MatchTable0[] = {
>     GIM_Try, /*On fail goto*//*Label 0*/ 74, // Rule ID 0 //
>       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
>       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ANYEXT,
>       // MIs[0] dst
>       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
>       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
>       // MIs[0] in
>       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
>       // (anyext:{ *:[i32] } i8:{ *:[i8] }:$in)  =>  (SELECT_I4:{ *:[i32] } ?:{ *:[i8] }:$in, (LI:{ *:[i32] } 1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }))
>       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
>       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
>       GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::LI,
>       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
>       GIR_AddImm, /*InsnID*/2, /*Imm*/0,
>       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
>       GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::LI,
>       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
>       GIR_AddImm, /*InsnID*/1, /*Imm*/1,
>       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
>       GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SELECT_I4,
>       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
>       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
>       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
>       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
>       GIR_EraseFromParent, /*InsnID*/0,
>       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
>       // GIR_Coverage, 0,
>       GIR_Done,
>     // Label 0: @74
>     GIM_Reject,
>     };
> ```
I meant more where that gets emitted in the emitter code, not the output


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141247/new/

https://reviews.llvm.org/D141247