[llvm] 42a5dda - [RISCV] Add more testcases for overflow-intrinsics.ll

[via llvm-commits]

Author: LiaoChunyu
Date: 2023-03-09T09:13:30+08:00
New Revision: 42a5dda553e84da98cb03630130e4820e93af8f2

URL: https://github.com/llvm/llvm-project/commit/42a5dda553e84da98cb03630130e4820e93af8f2
DIFF: https://github.com/llvm/llvm-project/commit/42a5dda553e84da98cb03630130e4820e93af8f2.diff

LOG: [RISCV] Add more testcases for overflow-intrinsics.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
index fea0199c8cfec..9b874370d5107 100644
--- a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
@@ -1281,3 +1281,41 @@ exit:
   ret void
 }
 
+define i16 @overflow_not_used(i16 %a, i16 %b, ptr %res) nounwind ssp {
+; RV32-LABEL: overflow_not_used:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a3, 16
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    and a4, a1, a3
+; RV32-NEXT:    add a0, a4, a0
+; RV32-NEXT:    and a3, a0, a3
+; RV32-NEXT:    bne a3, a0, .LBB37_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    li a1, 42
+; RV32-NEXT:  .LBB37_2:
+; RV32-NEXT:    sh a0, 0(a2)
+; RV32-NEXT:    mv a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: overflow_not_used:
+; RV64:       # %bb.0:
+; RV64-NEXT:    lui a3, 16
+; RV64-NEXT:    addiw a3, a3, -1
+; RV64-NEXT:    and a0, a0, a3
+; RV64-NEXT:    and a4, a1, a3
+; RV64-NEXT:    add a0, a4, a0
+; RV64-NEXT:    and a3, a0, a3
+; RV64-NEXT:    bne a3, a0, .LBB37_2
+; RV64-NEXT:  # %bb.1:
+; RV64-NEXT:    li a1, 42
+; RV64-NEXT:  .LBB37_2:
+; RV64-NEXT:    sh a0, 0(a2)
+; RV64-NEXT:    mv a0, a1
+; RV64-NEXT:    ret
+  %add = add i16 %b, %a
+  %cmp = icmp ult i16 %add, %b
+  %Q = select i1 %cmp, i16 %b, i16 42
+  store i16 %add, ptr %res
+  ret i16 %Q
+}