[PATCH] D145205: [codegen][riscv] Emit CFI directives when using shadow call stack
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 8 14:30:37 PST 2023
jrtc27 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:86
+ dwarf::DW_CFA_val_expression,
+ 18, // register
+ 2, // length
----------------
getDwarfRegNum with SCSPReg
================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:87
+ 18, // register
+ 2, // length
+ static_cast<char>(unsigned(dwarf::DW_OP_breg18)),
----------------
Similarly don't hard-code (up to you whether you unconditionally use bregx or branch on whether reg num is < 32)
================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:89
+ static_cast<char>(unsigned(dwarf::DW_OP_breg18)),
+ static_cast<char>(-SlotSize & 0x7f), // addend (sleb128)
+ };
----------------
AArch64 does the cast before the mask, should be consistent
================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:149
+ unsigned CFIIndex =
+ MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, 18));
+ BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
----------------
Also don't hard-code
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D145205/new/
https://reviews.llvm.org/D145205
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