[PATCH] D145022: [RISCV] Add vsseg intrinsic for fixed length vectors

[Luke Lau via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd610c6c9c735: [RISCV] Add vsseg intrinsic for fixed length vectors (authored by luke).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145022/new/

https://reviews.llvm.org/D145022

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-store.ll

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