[PATCH] D145578: [AArch64] Cost-model vector splat LD1Rs to avoid unprofitable SLP vectorisation

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: dmgreen, fhahn.
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This slightly increases the costs of InsertElement instructions that are part of  a vector splat sequence, i.e. a load, InsertElement and a shuffle. The resulting LD1R is a high latency instruction, and this slight increase in costs avoids  SLP vectorisation for a couple of cases where this isn't profitable.

SPEC 2017 FP and INT performance results with this change are completely neutral so only seem to affect cases like the changed regression tests.

Fixes: https://github.com/llvm/llvm-project/issues/61047


https://reviews.llvm.org/D145578

Files:
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll

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