[PATCH] D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode

[lizhijin via Phabricator via llvm-commits]

lizhijin created this revision.
lizhijin added reviewers: paulwalker-arm, sdesmalen, david-arm, efriedma, kmclaughlin.
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This patch adds patterns to reduce redundant mov and sel instructions
for shift intrinsics with FalseLanesZero mode, when
FeatureExperimentalZeroingPseudosis supported.

      

For example, before:

  mov     z1.b, #0
  sel     z0.b, p0, z0.b, z1.b
  asr     z0.b, p0/m, z0.b, #7

After:

  movprfx z0.b, p0/z, z0.b
  asr     z0.b, p0/m, z0.b, #7


https://reviews.llvm.org/D145551

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm-zero.ll

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