[PATCH] D145548: [IR][DAG][RISCV] Allow scalable vector ISD::STRICT_FP_EXTEND and RISC-V supports for vector ISD::STRICT_FP_EXTEND.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:252
   FP_EXTEND_VL,
+  STRICT_FP_EXTEND_VL,
 
----------------
There's a special place in the enum for STRICT opcodes. Look for `STRICT_FCVT_WU_RV64`.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1852
     defvar fwti = fvtiToFWti.Wti;
-    def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1),
-                                              (fvti.Mask V0),
-                                              VLOpFrag)),
+    def : Pat<(fwti.Vector (riscv_fpextend_vl
+                               (fvti.Vector fvti.RegClass:$rs1),
----------------
Can we use `any_riscv_fpextend_vl`?


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https://reviews.llvm.org/D145548