[PATCH] D145471: [RISCV] Set how many bytes load from or store to stack slot

Jim Lin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 7 23:02:56 PST 2023


Jim marked 3 inline comments as done.
Jim added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:82
+                                             int &FrameIndex,
+                                             unsigned &MemBytes) const {
   switch (MI.getOpcode()) {
----------------
craig.topper wrote:
> kito-cheng wrote:
> > We might need to init MemByte to 0?
> > 
> > ```
> >   /// Optional extension of isLoadFromStackSlot that returns the number of
> >   /// bytes loaded from the stack. This must be implemented if a backend
> >   /// supports partial stack slot spills/loads to further disambiguate
> >   /// what the load does.
> >   virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 
> >                                        int &FrameIndex,
> >                                        unsigned &MemBytes) const {
> >     MemBytes = 0; 
> >     return isLoadFromStackSlot(MI, FrameIndex);
> >   }
> > 
> > ```
> Do the callers care in the cases this function returns 0? Looks like MemBytes will be explicitly set on any path that returns a non-zero value.
It seems caller doesn't care MemBytes if the return value is zero (means it's not a load from or store to stack slot instruction).


================
Comment at: llvm/test/CodeGen/RISCV/stack-slot-coloring.mir:1
+# RUN: llc -march=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s
+
----------------
jrtc27 wrote:
> Can we update_mir_test_checks.py this, precommit and see the diff in this patch?
Add pre-commit test case


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D145471/new/

https://reviews.llvm.org/D145471



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