[PATCH] D145546: [RISCV] Enable subreg liveness by default

[Piyou Chen via Phabricator via llvm-commits]

BeMg created this revision.
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BeMg requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145546

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
  llvm/test/CodeGen/RISCV/shuffle-reverse.ll