[PATCH] D140460: [RISCV][MC] Add FLI instruction support for the experimental zfa extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:400
+static inline int getLoadFP32Imm(const APInt &Imm) {
+  if ((Imm.extractBitsAsZExtValue(9, 23) == 0b001110001 &&
+       Imm.extractBitsAsZExtValue(23, 0) == 0) ||
----------------
This hack to support the f16 minimum value causes this to miscompile.

```
; FIXME: This is the f16 minimum value. It should not be supported for f32.
define float @loadfpimm10() {
; CHECK-LABEL: loadfpimm10:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fli.s fa0, min
; CHECK-NEXT:    ret
  ret float 0.00006103515625
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140460/new/

https://reviews.llvm.org/D140460