[PATCH] D145485: [IR] Generalize interleave/deinterleave intrinsics to factors > 2
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 7 03:54:35 PST 2023
luke added inline comments.
================
Comment at: llvm/include/llvm/IR/Intrinsics.td:2120-2128
-
-def int_experimental_vector_interleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMHalfElementsVectorType<0>,
- LLVMHalfElementsVectorType<0>],
+def int_experimental_vector_interleave : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [llvm_vararg_ty],
[IntrNoMem]>;
-def int_experimental_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>,
----------------
This is the main disadvantage of using just one intrinsic to represent all factors: We have to use variadic arguments which complicates the type signature, and we need to do the verification ourselves in Verifier.cpp.
I also considered just creating separate intrinsics for each interleave factor, but didn't like the duplication that would be required in `Legalise*Types.cpp`/`SelectionDAGBuilder.cpp`.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D145485/new/
https://reviews.llvm.org/D145485
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