[PATCH] D144010: [X86] AMD Znver4 (Genoa) Scheduler enablement

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Thanks @GGanesh - I think if we can update the vector integer classes as well this will be good enough as an initial  commit and merging for 16.x



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Comment at: llvm/lib/Target/X86/X86ScheduleZnver4.td:1144
+defm : Zn4WriteResYMMPair<WriteVecLogicY, [Zn4FPVMisc0123], 1, [1], 1>; // Vector integer and/or/xor logicals (YMM).
+defm : Zn4WriteResZMMPair<WriteVecLogicZ, [Zn4FPVMisc0123], 1, [1], 2>; // Vector integer and/or/xor logicals (ZMM).
+defm : Zn4WriteResXMMPair<WriteVecTest, [Zn4FPVAdd12, Zn4FPSt], 1, [1, 1], 2>;  // FIXME: latency not from llvm-exegesis // Vector integer TEST instructions.
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It looks like the integer classes still need the ZMM resource cycles adjustment


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https://reviews.llvm.org/D144010