[llvm] 3b1240e - [RISCV] Add classes to define SchedWrite list

[via llvm-commits]

Author: wangpc
Date: 2023-03-07T17:54:05+08:00
New Revision: 3b1240ea763d8c4a536af713ae1e6aad9c1f4da3

URL: https://github.com/llvm/llvm-project/commit/3b1240ea763d8c4a536af713ae1e6aad9c1f4da3
DIFF: https://github.com/llvm/llvm-project/commit/3b1240ea763d8c4a536af713ae1e6aad9c1f4da3.diff

LOG: [RISCV] Add classes to define SchedWrite list

SchedWrites are relevant to LMUL for most instructions, so we have
to enumerate all defined SchedWrites when defining ReadAdcance.
This patch adds some classes to simplify these definitions.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D145041

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVScheduleV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index ad3d4cdcbfdf6..faf690ae46fd5 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -45,12 +45,29 @@ multiclass LMULReadAdvanceImpl<string name, int val,
   }
 }
 
+// Define classes to define list containing all SchedWrites for each (name, LMUL)
+// pair for each LMUL in each of the SchedMxList variants above and name in
+// argument `names`. These classes can be used to construct a list of existing
+// definitions of writes corresponding to each (name, LMUL) pair, that are needed
+// by the ReadAdvance. For example:
+// ```
+//   defm "" : LMULReadAdvance<"ReadVIALUX", 1,
+//                             LMULSchedWriteList<["WriteVIMovVX"]>.value>;
+// ```
+class LMULSchedWriteListImpl<list<string> names, list<string> MxList> {
+  list<SchedWrite> value = !foldl([]<SchedWrite>,
+                                  !foreach(name, names,
+                                    !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))),
+                                  all, writes, !listconcat(all, writes));
+}
+
 multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
 multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
 multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
   : LMULWriteResImpl<name, resources>;
 multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
+class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
 
 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
@@ -58,6 +75,7 @@ multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
   : LMULWriteResImpl<name, resources>;
 multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
+class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
 
 multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
 multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
@@ -65,10 +83,12 @@ multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
   : LMULWriteResImpl<name, resources>;
 multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
+class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
 
 multiclass LMULSchedWritesFWRed<string name> : LMULSchedWritesImpl<name, SchedMxListFWRed>;
 multiclass LMULWriteResFWRed<string name, list<ProcResourceKind> resources>
   : LMULWriteResImpl<name, resources>;
+class LMULSchedWriteListFWRed<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFWRed>;
 
 
 // 3.6 Vector Byte Length vlenb