[llvm] 3a0d5d8 - [X86] Precommit a test

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2023-03-06T19:45:34-08:00
New Revision: 3a0d5d846a67cfe8454a537c72fba6f217d792c0

URL: https://github.com/llvm/llvm-project/commit/3a0d5d846a67cfe8454a537c72fba6f217d792c0
DIFF: https://github.com/llvm/llvm-project/commit/3a0d5d846a67cfe8454a537c72fba6f217d792c0.diff

LOG: [X86] Precommit a test

This patch precommits a test for:

https://github.com/llvm/llvm-project/issues/61073

Added: 
    llvm/test/CodeGen/X86/and-shift.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/and-shift.ll b/llvm/test/CodeGen/X86/and-shift.ll
new file mode 100644
index 000000000000..9626c627900f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/and-shift.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-unknown   | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
+
+define i32 @shift30_and2_i32(i32 %x) {
+; X32-LABEL: shift30_and2_i32:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $30, %eax
+; X32-NEXT:    andl $-2, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift30_and2_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $30, %eax
+; X64-NEXT:    andl $-2, %eax
+; X64-NEXT:    retq
+  %shr = lshr i32 %x, 30
+  %and = and i32 %shr, 2
+  ret i32 %and
+}
+
+define i64 @shift62_and2_i64(i64 %x) {
+; X32-LABEL: shift62_and2_i64:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $30, %eax
+; X32-NEXT:    andl $-2, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift62_and2_i64:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $62, %rax
+; X64-NEXT:    andl $-2, %eax
+; X64-NEXT:    retq
+  %shr = lshr i64 %x, 62
+  %and = and i64 %shr, 2
+  ret i64 %and
+}
+
+define i64 @shift30_and2_i64(i64 %x) {
+; X32-LABEL: shift30_and2_i64:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $30, %eax
+; X32-NEXT:    andl $-2, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift30_and2_i64:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $30, %rax
+; X64-NEXT:    andl $2, %eax
+; X64-NEXT:    retq
+  %shr = lshr i64 %x, 30
+  %and = and i64 %shr, 2
+  ret i64 %and
+}