[PATCH] D145353: [PowerPC] remove side effect for some cases for saturate instructions

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15789-15821
+    case ISD::INTRINSIC_W_CHAIN: {
+      unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+      if (IID == Intrinsic::ppc_altivec_vsum4sbs ||
+          IID == Intrinsic::ppc_altivec_vsum4shs ||
+          IID == Intrinsic::ppc_altivec_vsum4ubs) {
+        if (BuildVectorSDNode *BVN =
+                dyn_cast<BuildVectorSDNode>(N->getOperand(3))) {
----------------
Can you please do the following two things:
1. Add a comment explaining that these sum-across intrinsics only have a chain due to the side effects. If we know that the SAT bit will not be set, we can replace any uses of their chain with the input chain.
2. Combine these into a single switch - along the lines of:
```
switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
case Intrinsic::ppc_vsx_lxvw4x:
case Intrinsic::ppc_vsx_lxvd2x:
  if (Subtarget.needsSwapsForVSXMemOps())
    return expandVSXLoadForLE(N, DCI);
  break;
case Intrinsic::ppc_altivec_vsum4sbs:
case Intrinsic::ppc_altivec_vsum4shs:
case Intrinsic::ppc_altivec_vsum4ubs: {
  // handle the chain replacement
}
}
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D145353/new/

https://reviews.llvm.org/D145353