[PATCH] D144388: [X86] Revise Alderlake P-Core schedule model

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D144388#4170591 <https://reviews.llvm.org/D144388#4170591>, @HaohaiWen wrote:

> Should we always use worst latency in schedule model like TTI?

This might be necessary - I hit something similar in https://github.com/llvm/llvm-project/issues/61002 where <2 x float> fdiv operations ended up trashing perf because of the strange floatbits in the other vector elements.

It'd be an interesting future project to add support to the models for more special cases like back-2-back ops though (IIRC many CPUs have similar cases for chains of FMAs etc.).

I don't like the idea of blindly taking the uops.info (or Agner or instlatx64 or Intel/AMD) numbers as a golden truth though - we need to be careful about automating scheduler model generation, even though manual reviews/edits are very tedious....


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