[PATCH] D145299: [X86] Generate better code for std::bit_ceil

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added a comment.

In D145299#4169706 <https://reviews.llvm.org/D145299#4169706>, @spatel wrote:

> In D145299#4169702 <https://reviews.llvm.org/D145299#4169702>, @RKSimon wrote:
>
>> What is preventing is from performing this in InstCombine? I don't think this pattern will emerge in SelectionDAG
>
> I haven't found a way to avoid a poison shift in IR without doing a cmp+select or umax yet. I think we're relying on the x86-specific behavior of masking the shift amount to make that part of the logic disappear in this patch.

The IR is:

  %2 = add i32 %0, -1
  %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false), !range !5
  %4 = sub nuw nsw i32 32, %3
  %5 = shl nuw i32 1, %4
  %6 = icmp ugt i32 %0, 1
  %7 = select i1 %6, i32 %5, i32 1
  ret i32 %7

The poison shift is if `%3` is zero? (which I think is actually UB in `std::bit_ceil`)


Repository:
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https://reviews.llvm.org/D145299