[PATCH] D145085: [RISCV] Lower interleaved accesses

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:14878
+  MVT VT =
+      getContainerForFixedLengthVector(getValueType(DL, VTy).getSimpleVT());
+  RISCVII::VLMUL LMUL = getLMUL(VT);
----------------
Save the result of getValueType from the earlier call.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:14881
+  unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
+  if (IsVsseg) {
+    const RISCV::VSSEGPseudo *P =
----------------
Would it be sufficient to just check LMul * Factor is <= 8 instead of looking up the pseudos?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:14922
+
+  Intrinsic::ID FixedLenIntrIds[] = {
+      Intrinsic::riscv_seg2_load, Intrinsic::riscv_seg3_load,
----------------
`static const`?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:14974
+
+  Intrinsic::ID FixedLenIntrIds[] = {
+      Intrinsic::riscv_seg2_store, Intrinsic::riscv_seg3_store,
----------------
`static const`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D145085/new/

https://reviews.llvm.org/D145085